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ORCIDTianzhu Xiong
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2020 – today
- 2025
[j7]Tianzhu Xiong
, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 52-65 (2025)- 2024
- [j6]Chenchen Deng, Tianzhu Xiong, Zhaoshi Li, Zhiwei Liu, Yao Wang, Jianfeng Zhu, Jun Yang, Shaojun Wei, Leibo Liu:
CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. Sci. China Inf. Sci. 67(4) (2024) - [j5]Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng:
An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. Microelectron. J. 151: 106308 (2024) - [j4]Jinwu Chen, Yitong Zhao, Tianzhu Xiong, Xin Si:
An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1371-1375 (2024) - [j3]Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si:
Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3181-3185 (2024) - [j2]Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si:
A 22-nm 264-GOPS/mm2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32(12): 2389-2393 (2024) - [c11]Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si:
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. CICC 2024: 1-2 - [c10]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - 2023
- [j1]Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang:
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci. China Inf. Sci. 66(10) (2023) - [c9]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c8]Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang:
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC 2023: 134-135 - 2022
- [c7]Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang:
A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. APCCAS 2022: 501-504 - [c6]An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang:
ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. ISCAS 2022: 2276-2280 - [c5]Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si:
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS 2022: 3383-3387 - [c4]Jinwu Chen, Tianzhu Xiong, Xin Si:
A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices. MCSoC 2022: 153-158 - 2021
- [c3]Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang:
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC 2021: 195-196 - [c2]Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si:
Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. UCET 2021: 47-52 - 2020
- [c1]Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu:
CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. MICRO 2020: 342-355
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