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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 33
Volume 33, Number 1, January 2025
- Hyoseok Song, Kwangmin Kim, Gain Kim, Byungsub Kim:
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. 1-9 - Jie Ding, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu:
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. 10-20 - Haitao Du, Hairui Zhu, Song Chen, Yi Kang:
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. 21-34 - Haiyue Yan, Yan Ye, Wenjia Li, Xuefei Bai:
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications. 35-46 - Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu:
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. 47-51 - Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. 52-65 - Zhen Gao, Yanmao Qi, Jinchang Shi, Qiang Liu, Guangjun Ge, Yu Wang, Pedro Reviriego:
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. 66-74 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution. 75-87 - Jie Li, Chuanlun Zhang, Wenxuan Yang, Heng Li, Xiaoyan Wang, Chuanjun Zhao, Shuangli Du, Yiguang Liu:
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation. 88-101 - Zhichao Chen, Ali H. Hassan, Rhesa Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta:
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. 102-113 - Anawin Opasatian, Makoto Ikeda:
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier. 114-127 - Ken Li, Tian Xie, Tzu-Han Wang, Shaolan Li:
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. 128-139 - Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, Zhaori Bi:
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. 140-153 - Jinghai Wang, Shanlin Xiao, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu:
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. 154-167 - Jhe-En Lin, Shen-Iuan Liu:
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. 168-178 - Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam:
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory. 179-192 - Dongkwun Kim, Zhaoqing Wang, Paul Xuanyuanliang Huang, Pavan Kumar Chundi, Suhwan Kim, Andres A. Blanco, Ram K. Krishnamurthy, Mingoo Seok:
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor. 193-206 - Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. 207-220 - Zhe Huang, Xingyao Chen, Feng Gao, Ruige Li, Xiguang Wu, Fan Zhang:
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V. 221-233 - Zhaolin Yang, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. 234-247 - Shuming Guo, Yinyin Lin, Hao Wang, Yao Li, Chongyan Gu, Weiqiang Liu, Yijun Cui:
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. 248-260 - Xingye Liu, Paul Ampadu:
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation. 261-274 - Alexandre Almeida da Silva, Lucas Nogueira, Alexandre Coelho, Jarbas A. N. Silveira, César A. M. Marcon:
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC. 275-287 - Lakshmi Bhanuprakash Reddy Konduru, Vikramkumar Pudi, Balasubramanyam Appina:
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. 288-292 - Zhihao Zhou, Wei Zhang, Xinyi Guo, Jianhan Zhao, Yanyan Liu:
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes. 293-297 - Yiwei Chang, Zhichuan Guo:
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks. 298-302
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last updated on 2025-01-22 20:30 CET by the dblp team
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