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ORCIDVikramkumar Pudi
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2020 – today
- 2025
[j10]Lakshmi Bhanuprakash Reddy Konduru
, Vikramkumar Pudi, Balasubramanyam Appina:
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 288-292 (2025)- 2024
- [j9]K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Balasubramanyam Appina, Anupam Chattopadhyay:
Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2799-2803 (2024) - [c20]Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi:
Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics. ISCAS 2024: 1-5 - 2023
- [c19]Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi:
Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs. APCCAS 2023: 299-303 - [c18]Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi, Naga Teja Babu M:
A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips. ISCAS 2023: 1-5 - [c17]Keerthija Puli, Vikramkumar Pudi:
Design of Low Power ALU for RISC-VISA. iSES 2023: 37-42 - [c16]K. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi:
Design of Energy Efficient and Low Delay Posit Multiplier. VLSID 2023: 1-6 - 2022
- [j8]Vijaya Lakshmi, John Reuben, Vikramkumar Pudi:
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1148-1158 (2022) - [j7]Vijaya Lakshmi, Vikramkumar Pudi, John Reuben:
Inner Product Computation In-Memory Using Distributed Arithmetic. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4546-4557 (2022) - [i1]Ambati Sathvik, Tirunagari Rahul, Anubhab Baksi, Vikramkumar Pudi:
Hardware Implementation of SpoC-128. IACR Cryptol. ePrint Arch. 2022: 119 (2022) - 2021
- [c15]K. B. Dheeraj Kumar, K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Srinivasu Bodapati:
Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs. iSES 2021: 139-142 - [c14]K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi:
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. VDAT 2021: 1-4 - 2020
- [j6]Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Duo Chen, Rosa Q. So, Anupam Chattopadhyay, Cuntai Guan:
A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning. IEEE Consumer Electron. Mag. 9(3): 90-96 (2020) - [c13]Vikramkumar Pudi, Srinivasu Bodapati, Sachin Kumar, Anupam Chattopadhyay:
Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management. iSES 2020: 103-108
2010 – 2019
- 2019
- [j5]Tingting Zhang, Vikramkumar Pudi, Weiqiang Liu:
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1232-1236 (2019) - [c12]Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay:
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. ISQED 2019: 216-223 - [c11]Sai Praveen Kadiyala, Vikram Kumar Pudi, Mohit Garg, Hau T. Ngo, Siew-Kei Lam, Thambipillai Srikanthan:
Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images. SoCC 2019: 224-229 - 2018
- [j4]Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam:
Secure and Lightweight Compressive Sensing Using Stream Cipher. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 371-375 (2018) - [c10]B. Srinivasu, Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam:
CoLPUF : A Novel Configurable LFSR-based PUF. APCCAS 2018: 358-361 - [c9]Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam:
Efficient and Lightweight Quantized Compressive Sensing using μ-Law. ISCAS 2018: 1-5 - [c8]Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay:
Lightweight ASIC Implementation of AEGIS-128. ISVLSI 2018: 251-256 - [c7]Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay:
An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning. ISVLSI 2018: 726-731 - [c6]Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay:
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. VLSI-SoC 2018: 95-100 - [c5]Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici:
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. VLSID 2018: 398-403 - 2017
- [j3]Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi:
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. IEEE Trans. Computers 66(10): 1824-1830 (2017) - [c4]Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay:
SHA-3 implementation using ReRAM based in-memory computing architecture. ISQED 2017: 325-330 - [c3]Sai Praveen Kadiyala, Vikram Kumar Pudi, Siew-Kei Lam:
Approximate compressed sensing for hardware-efficient image compression. SoCC 2017: 340-345 - 2016
- [c2]Vikramkumar Pudi, Anupam Chattopadhyay, Thambipillai Srikanthan:
Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices. ISIC 2016: 1-4 - [c1]Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan:
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. ISVLSI 2016: 18-23 - 2015
- [j2]Tahiyah Nou Shene, Vikramkumar Pudi, K. Sridharan, Vineetha Thomas, J. Arthi:
Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle. IET Comput. Vis. 9(4): 559-569 (2015) - [j1]Vikramkumar Pudi, K. Sridharan:
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2352-2356 (2015)
Coauthor Index
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