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ORCIDVLSI-SoC 2018: Verona, Italy
- IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. IEEE 2018, ISBN 978-1-5386-4756-1
Session 1: Emerging technologies and computing paradigms
- Swagata Mandal, Debjyoti Bhattacharjee
, Yaswanth Tavva, Anupam Chattopadhyay:
ReRAM-based In-Memory Computation of Galois Field arithmetic. 1-6 - Md. Adnan Zaman, Srinivas Katkoori:
Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations. 7-12 - Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang:
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips. 13-18 - Francesco Barchi, Gianvito Urgese, Andrea Acquaviva, Enrico Macii:
Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture. 19-24
Session 2: Digital architectures: NoC, multi- and many-core, hybrid, and reconfigurable
- Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini:
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. 25-30 - Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese:
A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration. 31-36 - Shahzad Muzaffar, Ibrahim Abe M. Elfadel:
An Instruction Set Architecture for Low-power, Dynamic IoT Communication. 37-42
Session 3: Prototyping, verification, modeling, and simulation: from digital to analog circuits
- Pasquale Davide Schiavone, Ernesto Sánchez, Annachiara Ruospo, Francesco Minervini, Florian Zaruba, Germain Haugou, Luca Benini:
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. 43-48 - Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu:
On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields. 49-54 - Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. 55-58
Session 4: Variability, reliability, and test
- Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez, Matteo Sonza Reorda, Jan-Gerd Mess:
An analysis of test solutions for COTS-based systems in space applications. 59-64 - Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac:
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. 65-70 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements. 71-76 - Zahira Perez, Hector Villacorta, Víctor H. Champac:
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. 77-82
Session 5: Hardware security
- Suyuan Chen, Ranga Vemuri:
On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits. 83-88 - Konstantin Braun, Tim Fritzmann, Georg Maringer, Thomas Schamberger, Johanna Sepúlveda:
Secure and Compact Full NTRU Hardware Implementation. 89-94 - Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay:
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. 95-100 - Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos:
Low-budget Energy Sector Cyberattacks via Open Source Exploitation. 101-106
Session 6: Machine learning and emerging technologies for low-power and energy-efficient SoC design
- Edouard Giacomin, Pierre-Emmanuel Gaillardon:
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. 107-112 - Valentino Peluso, Andrea Calimera:
Energy-Driven Precision Scaling for Fixed-Point ConvNets. 113-118
Session 7: Embedded and cyberphysical systems: architecture, design, and software
- Stefano Aldegheri, Silvia Manzato, Nicola Bombieri:
Enhancing Performance of Computer Vision Applications on Low-Power Embedded Systems Through Heterogeneous Parallel Programming. 119-124 - Luiz Antonio de Oliveira Junior, Edna Barros:
An FPGA-based Hardware Accelerator for Scene Text Character Recognition. 125-130 - Rahul Shrestha, Ashutosh Sharma:
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. 131-136
Session 8: CAD: Synthesis and analysis
- Anna Bernasconi, Antonio Boffa, Fabrizio Luccio, Linda Pagli:
Two Combinatorial Problems on the Layout of Switching Lattices. 137-142 - Luca Stornaiuolo, Marco Rabozzi, Donatella Sciuto, Marco D. Santambrogio, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu:
HLS Support for Polymorphic Parallel Memories. 143-148 - Valerio Tenace, Andrea Calimera:
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. 149-154
Special Session 1: IoT for health, wellness and personal assistance
- Reza Ranjandish, Alexandre Schmid:
Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical Neuromodulation. 155-158 - Marc Souchaud, Pierre Jacob, Camille Simon Chane, Aymeric Histace, Olivier Romain, Maurice Tchuenté, Denis Sereno:
Mobile Phones Hematophagous Diptera Surveillance in the field using Deep Learning and Wing Interference Patterns. 159-162 - Julien Le Kernec, Francesco Fioranelli, Shufan Yang, Jordane Lorandel, Olivier Romain:
Radar for assisted living in the context of Internet of Things for Health and beyond. 163-167 - Achraf Lamlih, Philippe Freitas, Mohamed Moez Belhaj, Jérémie Salles, Vincent Kerzerho, Fabien Soulier, Serge Bernard, Tristan Rouyer, Sylvain Bonhommeau:
A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties. 168-171
Special Session 2: Design understanding
- Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener:
Design Understanding: From Logic to Specification*. 172-175
Special Session 3: Neuromorphic computing - from robust hardware architectures to testing strategies
- Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena Ioana Vatajelu, Elisa Vianello:
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies. 176-179
Special Session 4: Non-volatile emerging memories - breaking down the memory wall
- Ian O'Connor, Mayeul Cantan, Cédric Marchand, Bertrand Vilquin, Stefan Slesazeck, Evelyn T. Breyer, Halid Mulaosmanovic, Thomas Mikolajick, Bastien Giraud, Jean-Philippe Noel, Adrian M. Ionescu, Igor Stolichnov:
Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices. 180-183 - Erya Deng, Zhaohao Wang, Wang Kang, Shaoqian Wei, Weisheng Zhao:
Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM. 184-187 - Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat:
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip. 188-191 - Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel:
Reliable ReRAM-based Logic Operations for Computing in Memory. 192-195
Poster Session
- Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa:
An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. 196-200 - Mubashir Hussain, Hui Guo:
A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC. 201-206 - Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. 207-212 - Anna Bernasconi, Valentina Ciriani, Luca Frontini:
Testability of Switching Lattices in the Stuck at Fault Model. 213-218 - Muhammad Awais, Hassan Ghasemzadeh Mohammadi, Marco Platzner:
An MCTS-based Framework for Synthesis of Approximate Circuits. 219-224 - Steve Bigalke, Jens Lienig:
FLUTE-EM: Electromigration-Optimized Net Considering Topology Currents and Mechanical Stress. 225-230 - Keerthikumara Devarajegowda, Wolfgang Ecker:
Meta-model Based Automation of Properties for Pre-Silicon Verification. 231-236 - Stefano Centomo, Marco Panato, Franco Fummi:
Cyber-Physical Systems Integration in a Production Line Simulator. 237-242 - Yakup Murat:
Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder. 243-248 - Florenc Demrozi, Kevin Costa, Federico Tramarin, Graziano Pravadelli:
A graph-based approach for mobile localization exploiting real and virtual landmarks. 249-254 - Mahdi Tala, Davide Bertozzi:
Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization. 255-260 - Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen:
Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA. 261-266 - Gionata Benelli, Gabriele Meoni, Luca Fanucci:
A low power keyword spotting algorithm for memory constrained embedded systems. 267-272
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