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ORCIDJean-Michel Portal
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- affiliation: Aix-Marseille University (AMU), France
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2020 – today
- 2024
[i19]Clement Türck, Kamel-Eddine Harabi, Adrien Pontlevy, Théo Ballet, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
The Logarithmic Memristor-Based Bayesian Machine. CoRR abs/2406.03492 (2024)- [i18]Nikhil Garg, Davide Florini, Patrick Dufour, Eloi Muhr, Mathieu-Coumba Faye, Marc Bocquet, Damien Querlioz, Yann Beilliard, Dominique Drouin, Fabien Alibart, Jean-Michel Portal:
Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits. CoRR abs/2406.19667 (2024) - 2023
- [c108]Kamel-Eddine Harabi, Clement Türck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal:
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. ASP-DAC 2023: 184-185 - [c107]Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Binary ReRAM-based BNN first-layer implementation. DATE 2023: 1-6 - [c106]Clement Türck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors. DATE 2023: 1-2 - [c105]Joel Minguet Lopez, Manon Dampfhoffer
, Tifenn Hirtzlin, Lucas Reganaz, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Thomas Magis, Catherine Carabasse, Niccolo Castellani, Valentina Meli, Elisa Vianello, Damien Deleruyelle, Jean-Michel Portal, Gabriel Molas, François Andrieu:
1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation. MIXDES 2023: 1-6 - [i17]Kamel-Eddine Harabi, Clement Türck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal:
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. CoRR abs/2302.14577 (2023) - [i16]Fadi Jebali, Atreya Majumdar, Clement Türck, Kamel-Eddine Harabi, Mathieu-Coumba Faye, Eloi Muhr, Jean-Pierre Walder, Oleksandr Bilousov, Amadeo Michaud, Elisa Vianello, Tifenn Hirtzlin, François Andrieu, Marc Bocquet, Stéphane Collin, Damien Querlioz, Jean-Michel Portal:
Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell. CoRR abs/2305.12875 (2023) - 2022
- [j28]Eduardo Esmanhotto, Tifenn Hirtzlin, Djohan Bonnet, Niccolo Castellani, Jean-Michel Portal, Damien Querlioz, Elisa Vianello:
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. Adv. Intell. Syst. 4(11) (2022) - [j27]Eduardo Esmanhotto, Tifenn Hirtzlin, Djohan Bonnet, Niccolo Castellani, Jean-Michel Portal, Damien Querlioz, Elisa Vianello:
Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. Adv. Intell. Syst. 4(11) (2022) - [c104]Joel Minguet Lopez, François Rummens, Lucas Reganaz, A. Heraud, Tifenn Hirtzlin, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Niccolo Castellani, Valentina Meli, S. Martin, Thomas Magis, Elisa Vianello, C. Sabbione, Damien Deleruyelle, Marc Bocquet, Jean-Michel Portal, Gabriel Molas, François Andrieu:
1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing. IMW 2022: 1-4 - [c103]Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-François Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello:
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. IRPS 2022: 8-1 - [i15]Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-Francois Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello:
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. CoRR abs/2203.01680 (2022) - [i14]Nikhil Garg, Ismael Balafrej, Terrence C. Stewart, Jean-Michel Portal, Marc Bocquet, Damien Querlioz, Dominique Drouin, Jean Rouat, Yann Beilliard, Fabien Alibart:
Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential. CoRR abs/2203.11022 (2022) - 2021
- [j26]Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 138-147 (2021) - [c102]Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE 2021: 1-6 - [c101]Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSCIRC 2021: 83-86 - [c100]Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSDERC 2021: 83-86 - [c99]Joel Minguet Lopez, Niccolo Castellani, Laurent Grenouillet, Lucas Reganaz, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Thomas Magis, Damien Deleruyelle, Marc Bocquet, Jean-Michel Portal, Etienne Nowak, Gabriel Molas:
Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays. IMW 2021: 1-4 - [c98]Joel Minguet Lopez, Lucas Hudeley, Laurent Grenouillet, Diego Alfaro Robayo, Jury Sandrini, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Damien Deleruyelle, Niccolo Castellani, Marc Bocquet, Jean-Michel Portal, Etienne Nowak, Gabriel Molas:
Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization. IRPS 2021: 1-6 - [c97]Fadi Jebali, Atreya Majumdar, Axel Laborieux, Tifenn Hirtzlin, Elisa Vianello, Jean-Pierre Walder, Marc Bocquet, Damien Querlioz, Jean-Michel Portal:
CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks. MWSCAS 2021: 158-161 - [c96]J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal:
A Self-referenced and regulated sensing solution for PCM with OTS selector. VLSI-SoC 2021: 1-6 - [c95]J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal:
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. VLSI-SoC (Selected Papers) 2021: 225-243 - [i13]Atreya Majumdar, Marc Bocquet, Tifenn Hirtzlin, Axel Laborieux, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks. CoRR abs/2107.06064 (2021) - [i12]Kamel-Eddine Harabi, Tifenn Hirtzlin, Clement Türck, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Jean-Michel Portal, Marc Bocquet, Damien Querlioz:
A Memristor-Based Bayesian Machine. CoRR abs/2112.10547 (2021) - 2020
- [j25]Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal:
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access 8: 109297-109308 (2020) - [c94]Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Liza Herrera Diez, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. AICAS 2020: 136-140 - [c93]Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. DATE 2020: 690-695 - [c92]Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud:
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE 2020: 1187-1192 - [c91]Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Embracing the Unreliability of Memory Devices for Neuromorphic Computing. IRPS 2020: 1-5 - [i11]Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Liza Herrera Diez, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. CoRR abs/2005.01973 (2020) - [i10]Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. CoRR abs/2006.11595 (2020) - [i9]Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Embracing the Unreliability of Memory Devices for Neuromorphic Computing. CoRR abs/2007.06238 (2020) - [i8]Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Implementation of Ternary Weights with Resistive RAM Using a Single Sense Operation per Synapse. CoRR abs/2007.14234 (2020) - [i7]Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu:
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR abs/2012.00061 (2020)
2010 – 2019
- 2019
- [j24]Tifenn Hirtzlin, Bogdan Penkovsky, Marc Bocquet, Jacques-Olivier Klein, Jean-Michel Portal, Damien Querlioz:
Stochastic Computing for Hardware Implementation of Binarized Neural Networks. IEEE Access 7: 76394-76403 (2019) - [j23]Mouhamad Alayan, Eloi Muhr, Alexandre Levisse, Marc Bocquet, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, Jean-Michel Portal:
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 748-752 (2019) - [c90]Tifenn Hirtzlin, Marc Bocquet, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks. AICAS 2019: 288-292 - [c89]Damien Querlioz, Julie Grollier, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Marc Bocquet, Jean-Michel Portal, Miguel Romera, Philippe Talatchian:
Memory-Centric Neuromorphic Computing With Nanodevices. BioCAS 2019: 1-4 - [c88]Mounia Kharbouche-Harrari, Romain Wacquez, Gregory di Pendina, Jean-Max Dutertre, Jérémy Postel-Pellerin, Driss Aboulkassimi, Jean-Michel Portal:
Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM. IOLTS 2019: 322-327 - [c87]Mounia Kharbouche-Harrari, Gregory di Pendina, Romain Wacquez, Bernard Dieny, Driss Aboulkassimi, Jérémy Postel-Pellerin, Jean-Michel Portal:
Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis. ISCAS 2019: 1-5 - [c86]Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein, Nicolas Locatelli, Adrien F. Vincent, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. NANOARCH 2019: 1-5 - [i6]Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks. CoRR abs/1902.02528 (2019) - [i5]Tifenn Hirtzlin, Marc Bocquet, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks. CoRR abs/1904.03652 (2019) - [i4]Tifenn Hirtzlin, Bogdan Penkovsky, Marc Bocquet, Jacques-Olivier Klein, Jean-Michel Portal, Damien Querlioz:
Stochastic Computing for Hardware Implementation of Binarized Neural Networks. CoRR abs/1906.00915 (2019) - [i3]Tifenn Hirtzlin, Marc Bocquet, Bogdan Penkovsky, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz:
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays. CoRR abs/1908.04066 (2019) - [i2]Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein, Nicolas Locatelli, Adrien F. Vincent, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. CoRR abs/1908.04085 (2019) - 2018
- [j22]Steve Ngueya W., Jean-Michel Portal, Hassen Aziza, Julien Mellier, Stephane Ricard:
An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories. J. Low Power Electron. 14(1): 157-169 (2018) - [c85]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS 2018: 1-6 - [c84]Elena Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat:
Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS 2018: 109-114 - [c83]Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal:
Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. IOLTS 2018: 243-244 - [c82]Thibault Kempf, Vincenzo Della Marca, L. Baron, F. Maugain, Francesco La Rosa, Stephan Niel, Arnaud Régnier, Jean-Michel Portal, Pascal Masson:
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. IRPS 2018: 6 - [c81]Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel:
Reliable ReRAM-based Logic Operations for Computing in Memory. VLSI-SoC 2018: 192-195 - 2017
- [j21]Steve Ngueya W., Jean-Michel Portal, Hassen Aziza, Julien Mellier, Stephane Ricard:
A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps. J. Low Power Electron. 13(4): 595-604 (2017) - [c80]Alexis Krakovinsky, Marc Bocquet, Romain Wacquez, Jean Coignus, Jean-Michel Portal:
Thermal laser attack and high temperature heating on HfO2-based OxRAM cells. IOLTS 2017: 85-89 - [c79]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - [c78]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
High density emerging resistive memories: What are the limits? LASCAS 2017: 1-4 - [c77]Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
Architecture, design and technology guidelines for crosspoint memories. NANOARCH 2017: 55-60 - [c76]Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza:
An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories. NGCAS 2017: 209-212 - [c75]Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza:
Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory. NORCAS 2017: 1-5 - [c74]Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza:
High voltage recycling scheme to improve power consumption of regulated charge pumps. PATMOS 2017: 1-5 - 2016
- [j20]Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal:
Optimization of a Particles Detection Chain Based on a VCO Structure. J. Electron. Test. 32(1): 21-30 (2016) - [j19]Hassen Aziza, Jean-Michel Portal:
Resistive RAM variability monitoring using a ring oscillator based test chip. Microelectron. Reliab. 64: 59-62 (2016) - [c73]Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet:
Multilevel operation in oxide based resistive RAM with SET voltage modulation. DTIS 2016: 1-5 - [c72]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal:
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH 2016: 7-12 - 2015
- [j18]Loic Welter, J. L. Scotto di Quaquero, Philippe Dreux, Laurent Lopez, Hassen Aziza, Jean-Michel Portal:
Improvement of MOSFET matching characterization with calibrated multiplexed test structure. Microelectron. Reliab. 55(9-10): 1328-1333 (2015) - [c71]Karine Coulié-Castellani, Wenceslas Rahajandraibe, Hassen Aziza, Jean-Michel Portal, Gilles Micolau:
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment. LATS 2015: 1-5 - [c70]Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver. LATS 2015: 1-4 - [c69]Jordan Innocenti, Franck Julien, Jean-Michel Portal, Laurent Lopez, Q. Hubert, Pascal Masson, Jacques Sonzogni, Stephan Niel, Arnaud Régnier:
Layout optimizations to decrease internal power and area in digital CMOS standard cells. MIPRO 2015: 1582-1587 - [c68]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS 2015: 1-4 - [c67]Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan:
Dynamic current reduction of CMOS digital circuits through design and process optimization. PATMOS 2015: 77-81 - 2014
- [j17]Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Coulié-Castellani, Jean-Michel Portal:
Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation. J. Low Power Electron. 10(1): 173-181 (2014) - [j16]Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, Marc Bocquet:
RRAM-based FPGA for "Normally Off, Instantly On" applications. J. Parallel Distributed Comput. 74(6): 2441-2451 (2014) - [j15]Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert:
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. 74(6): 2484-2496 (2014) - [j14]Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert:
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 443-454 (2014) - [c66]Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet:
Resistive memories: Which applications? DATE 2014: 1-6 - [c65]Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Jean-Michel Portal, Mathieu Moreau, Marc Bocquet:
Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability. DFT 2014: 81-85 - [c64]Loic Welter, Philippe Dreux, Jordan Innocenti, Hassen Aziza, Jean-Michel Portal:
Accurate multiplexed test structure for threshold voltage matching evaluation. DTIS 2014: 1-6 - [c63]Abdelali El Amraoui, Marc Bocquet, F. Barros, Jean-Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih, Vincent Fischer, Romain Coppard, R. Gwoziecky:
Printed complementary organic thin film transistors based decoder for ferroelectric memory. ESSCIRC 2014: 111-114 - [c62]Loic Welter, Philippe Dreux, Hassen Aziza, Jean-Michel Portal:
An innovative standard cells remapping method for in-circuit critical parameters monitoring. IOLTS 2014: 206-209 - [c61]Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal:
Improvement of a VCO concept for low energy particule detection and recognition. LATW 2014: 1-4 - [c60]Jordan Innocenti, Loic Welter, Franck Julien, Laurent Lopez, Jacques Sonzogni, Stephan Niel, Arnaud Régnier, Emmanuel Paire, Karen Labory, Eric Denis, Jean-Michel Portal, Pascal Masson:
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. MWSCAS 2014: 897-900 - [c59]Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Jean-Michel Portal, Bosko Nikolic, Lirida A. B. Naviner:
OxRAM-based non volatile flip-flop in 28nm FDSOI. NEWCAS 2014: 141-144 - 2013
- [j13]Hassen Aziza, Marc Bocquet, Jean-Michel Portal, Mathieu Moreau, Christophe Muller:
A novel test structure for OxRRAM process variability evaluation. Microelectron. Reliab. 53(9-11): 1208-1212 (2013) - [c58]Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal, Jamel Nebhen, Hervé Barthélemy:
Low-cost auto-calibration of passive polyphase filter in image reject receiver. ICECS 2013: 699-702 - [c57]Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller:
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. ICICDT 2013: 81-84 - [c56]Hassen Aziza, Marc Bocquet, Mathieu Moreau, Jean-Michel Portal:
Single-ended sense amplifier robustness evaluation for OxRRAM technology. IDT 2013: 1-5 - [c55]Loic Welter, Philippe Dreux, Jean-Michel Portal, Hassen Aziza:
Embedded high-precision frequency-based capacitor measurement system. IOLTS 2013: 116-121 - [c54]Santhosh Onkaraiah, Ogun Turkyilmaz, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller:
A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array. ISCAS 2013: 2440-2443 - [c53]Karine Castellani-Coulié, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Wenceslas Rahajandraibe, Christophe Muller:
SPICE level analysis of Single Event Effects in an OxRRAM cell. LATW 2013: 1-5 - [c52]Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver. LATW 2013: 1-4 - [c51]Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour:
DCG-FGT transistor: Retention study of Floating Gate charge. MWSCAS 2013: 825-827 - [c50]Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao:
Analytical study of complementary memristive synchronous logic gates. NANOARCH 2013: 70-75 - [c49]Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller:
Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS 2013: 1-4 - [c48]Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
On the investigation of built-in tuning of RF receivers using on-chip polyphase filters. VTS 2013: 1-6 - 2012
- [j12]Karine Castellani-Coulié, Hassen Aziza, Gilles Micolau, Jean-Michel Portal:
Optimization of SEU Simulations for SRAM Cells Reliability under Radiation. J. Electron. Test. 28(3): 331-338 (2012) - [j11]Jean-Michel Portal, Marc Bocquet, Damien Deleruyelle, Christophe Muller:
Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications. J. Low Power Electron. 8(1): 1-10 (2012) - [j10]Guillaume Just, Vincenzo Della Marca, Arnaud Régnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, Jean-Michel Portal, Pascal Masson:
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. J. Low Power Electron. 8(5): 717-724 (2012) - [c47]Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour:
PSP based DCG-FGT transistor Model: Full characterization procedure. ISCIT 2012: 222-227 - [c46]Karine Castellani-Coulié, Hassen Aziza, Wenceslas Rahajandraibe, Gilles Micolau, Jean-Michel Portal:
Investigation of a CMOS oscillator concept for particle detection and diagnosis. LATW 2012: 1-5 - [c45]Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring. LATW 2012: 1-5 - [c44]Gilles Micolau, Karine Castellani-Coulié, Hassen Aziza, Jean-Michel Portal:
SITARe: A simulation tool for analysis and diagnosis of radiation effects. LATW 2012: 1-5 - [c43]Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour:
A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT). MWSCAS 2012: 643-645 - [c42]Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller:
Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH 2012: 85-92 - [c41]Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, Marc Bocquet:
RRAM-based FPGA for "normally off, instantly on" applications. NANOARCH 2012: 101-108 - [c40]Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Hraziia, Costin Anghel, Amara Amara:
Bipolar ReRAM Based non-volatile flip-flops for low-power architectures. NEWCAS 2012: 417-420 - 2011
- [j9]Fabrice Rigaud, Jean-Michel Portal, Hassen Aziza, Didier Née, Julien Vast, Fabrice Argoud, Bertrand Borot:
Back-end soft and hard defect monitoring using a single test chip. Microelectron. Reliab. 51(6): 1136-1141 (2011) - [j8]Y. Joly, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Jean-Luc Ogier, Y. Bert, Franck Julien, Pascal Fornara:
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress. Microelectron. Reliab. 51(9-11): 1561-1563 (2011) - [c39]Christophe Muller, Damien Deleruyelle, Olivier Ginez, Jean-Michel Portal, Marc Bocquet:
Design challenges for prototypical and emerging memory concepts relying on resistance switching. CICC 2011: 1-7 - [c38]Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour:
PSP based DCG-FGT transistor model including characterization procedure. ICECS 2011: 228-231 - [c37]Hassen Aziza, Marc Bocquet, Jean-Michel Portal, Christophe Muller:
Bipolar OxRRAM memory array reliability evaluation based on fault injection. IDT 2011: 78-81 - [c36]Y. Joly, L. Truphemus, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Franck Julien, Pascal Fornara:
Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. ISCAS 2011: 2549-2552 - [c35]Karine Castellani-Coulié, Jean-Michel Portal, Gilles Micolau, Hassen Aziza:
Analysis of SEU parameters for the study of SRAM cells reliability under radiation. LATW 2011: 1-5 - [c34]Gilles Micolau, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal:
Impact of SEU configurations on a SRAM cell response at circuit level. LATW 2011: 1-5 - [c33]Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller:
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. NANOARCH 2011: 65-69
2000 – 2009
- 2009
- [c32]Olivier Ginez, Jean-Michel Portal, Hassen Aziza:
An on-line testing scheme for repairing purposes in Flash memories. DDECS 2009: 120-123 - [c31]Olivier Ginez, Jean-Michel Portal, Christophe Muller:
Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. ETS 2009: 61-66 - [c30]Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal:
Definition of an innovative filling structure for digital blocks : the DFM filler cell. ICECS 2009: 73-76 - 2008
- [j7]Hassen Aziza, Emmanuel Bergeret, Jean-Michel Portal, Olivier Ginez:
A Novel Low Power Oriented Design Methodology for Analog Blocks. J. Low Power Electron. 4(1): 60-67 (2008) - [c29]Manuel Sellier, Jean-Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy:
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ISQED 2008: 492-497 - [c28]Olivier Ginez, Jean-Michel Portal, Hassen Aziza:
A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. ITC 2008: 1-10 - [c27]Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal:
Metal filling impact on standard cells: definition of the metal fill corner concept. SBCCI 2008: 16-21 - 2007
- [i1]Laurent Lopez, Jean-Michel Portal, Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor. CoRR abs/0710.4736 (2007) - 2006
- [c26]B. Saillet, Arnaud Régnier, Jean-Michel Portal, B. Delsuc, Romain Laffont, Pascal Masson, Rachid Bouchakour:
MM11 based flash memory cell model including characterization procedure. ISCAS 2006 - 2005
- [j6]Jean-Michel Portal, Hassen Aziza, Didier Née:
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. J. Electron. Test. 21(1): 33-42 (2005) - [c25]Laurent Lopez, Jean-Michel Portal, Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor. DATE 2005: 462-463 - [c24]B. Saillet, Jean-Michel Portal, Didier Née:
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. DFT 2005: 131-139 - 2004
- [c23]Sandrine Bernardini, Jean-Michel Portal, Pascal Masson:
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. DATE 2004: 1404-1405 - [c22]Anna Labbé, Annie Pérez, Jean-Michel Portal:
Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. ISCAS (2) 2004: 637-640 - 2003
- [c21]Jean-Michel Portal, Hassen Aziza, Didier Née:
EEPROM Memory: Threshold Voltage Built In Self Diagnosis. ITC 2003: 23-28 - [c20]L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot:
Infrastructure IP for Back-End Yield Improvement. ITC 2003: 1129-1134 - 2002
- [c19]Jean-Michel Portal, L. Forli, Didier Née:
Floating-gate EEPROM cell: threshold voltage sensibility to geometry. ISCAS (1) 2002: 557-560 - [c18]Jean-Michel Portal, L. Forli, Didier Née:
Floating-gate EEPROM cell model based on MOS model 9. ISCAS (3) 2002: 799-802 - [c17]Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née:
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. ITC 2002: 31-36 - [c16]Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née:
An Automated Design Methodology for EEPROM Cell (ADE). MTDT 2002: 137-142 - 2001
- [j5]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. 17(3-4): 283-290 (2001) - [c15]Jean-Michel Portal, Annie Pérez:
Analyzing bridging faults impact on EEPROM cell array. ETW 2001: 3-8 - [c14]Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 - 2000
- [j4]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. 16(3): 289-299 (2000) - [j3]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. 16(5): 513-520 (2000) - [c13]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 - [c12]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80 - [c11]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Configuration Generation for FPGA Logic Cells. LATW 2000: 202-208 - [c10]Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI 2000: 3-8
1990 – 1999
- 1999
- [j2]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. 14(1-2): 159-167 (1999) - [c9]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368 - [c8]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622 - [c7]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW 1999: 146-151 - 1998
- [j1]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. 15(1): 45-50 (1998) - [c6]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271 - [c5]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88 - [c4]Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. DATE 1998: 89-94 - [c3]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148 - [c2]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111 - 1997
- [c1]Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-
Coauthor Index
[i19] [i18] [c108] [c107] [c106] [i17] [i16] [c104] [i14] [j26] [c101] [c100] [c99] [c98] [c97] [i13] [i12] [j25] [c94] [c93] [c91] [i11] [i10] [i9] [i8] [j24] [j23] [c90] [c89] [c86] [i6] [i5] [i4] [i3] [i2] [c84] [c83] [c81] [c80] [c73] [j16] [j15] [j14] [c66] [c65] [c63] [j13] [c56] [c53] [c50] [c49] [j11] [c42] [c41] [c40] [c39] [c37] [c33]
Jean-Philippe Noël
aka: Jean-Philippe Noel
aka: Jean-Philippe Noel
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