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ORCIDETW 2001: Stockholm, Sweden
- 6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001. IEEE Computer Society 2001, ISBN 0-7695-1017-5
- Jean-Michel Portal, Annie Pérez:
Analyzing bridging faults impact on EEPROM cell array. 3-8 - Yukiya Miura, Shuichi Seno:
Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. 9-16 - D. C. L. (Erik) van Geest, Frans G. M. de Jong:
System-level DFT for consumer products. 19-24 - Joonhwan Yi, John P. Hayes:
A fault model for function and delay testing. 27-34 - Herman J. Vermaak, Hans G. Kerkhoff:
Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations. 35-41 - Wilfried Daehn:
Demodulation based testing of off-chip driver performance. 42-47 - Oliver Niese, Tiziana Margaria
, Andreas Hagerer, Bernhard Steffen, Georg Brune, Werner Goerigk, Hans-Dieter Ide:
Automated regression testing of CTI-systems. 51-57 - Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff:
Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design. 61-67 - Daniela De Venuto, M. J. Ohletzo, Bruno Riccò:
On-chip signal level evaluation for mixed-signal ICs using digital window comparators. 68-72 - Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee:
The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case study. 73-78 - Mohsen Nahvi, André Ivanov:
A packet switching communication-based test access mechanism for system chips. 81-86 - Maisaa Khalil, Chantal Robach:
System level diagnosis - a comparison of two alternative approaches. 89-95 - Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL design validation, DFT and test pattern generation for high defects coverage. 99-105 - V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
An implementation for test-time reduction in VLIW transport-triggered architectures. 106-113 - René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On hardware generation of random single input change test sequences. 117-123 - Rainer Dorsch, Hans-Joachim Wunderlich:
Reusing scan chains for test pattern decompression. 124-132 - Marco Rona, Gunter Krampl:
A VHDL-based virtual test concept for pre-silicon test-program debug. 135-139 - Magnus Eckersand, Fredrik Franzon, Ken Filliter:
Using at-speed BIST to test LVDS serializer/deserializer function. 140-145
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