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2010 – 2019
- 2018
[j8]Changwon Choi, Hyungkeun Lee, Joonhwan Yi:
An interpolation method for strong barrel lens distortion. Vis. Comput. 34(11): 1479-1491 (2018)- 2016
- [j7]Joonhwan Yi, Hyungkeun Lee:
Modeling and performance analysis for a receiver-initiated MAC protocol in wireless sensor networks. Int. J. Distributed Sens. Networks 12(11) (2016) - [c4]Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin:
Register grouping for synthesis of clock gating logic. ICICDT 2016: 1-4 - 2015
- [j6]Joonhwan Yi, Jong-Gyu Kim:
Power modeling for digital circuits with clock gating. IEICE Electron. Express 12(24): 20150817 (2015) - [j5]Inhye Park, Joonhwan Yi, Hyungkeun Lee:
A Receiver-Initiated MAC Protocol for Wireless Sensor Networks Based on Tree Topology. Int. J. Distributed Sens. Networks 11: 950656:1-950656:10 (2015) - 2012
- [j4]Joonhwan Yi, John P. Hayes:
Robust Coupling Delay Test Sets. J. Electron. Test. 28(3): 375-388 (2012) - 2011
- [j3]Kyung Won Kim
, Joonhwan Yi, Seong-Jun Oh:
A data flow optimization method for high speed MAC processing in an IEEE 802.16m modem. IEICE Electron. Express 8(8): 530-535 (2011)
2000 – 2009
- 2007
- [c3]Junghee Lee, Joonhwan Yi:
Industrial experience with cycle error computation of cycle-accurate transaction level models. SoCC 2007: 155-158 - 2006
- [j2]Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 576-590 (2006) - [c2]Junghee Lee, Joonhwan Yi:
Cycle error correction in asynchronous clock modeling for cycle-based simulation. ASP-DAC 2006: 460-465 - 2005
- [j1]Joonhwan Yi, John P. Hayes:
The Coupling Model for Function and Delay Faults. J. Electron. Test. 21(6): 631-649 (2005) - 2002
- [b1]Joonhwan Yi:
High -level function and delay testing for digital circuits. University of Michigan, USA, 2002 - 2001
- [c1]Joonhwan Yi, John P. Hayes:
A fault model for function and delay testing. ETW 2001: 27-34
Coauthor Index
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