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ORCIDPascal Andreas Meinerzhagen
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2020 – today
- 2024
[j12]Axel Jantsch
, Swaroop Ghosh, Ümit Y. Ogras, Pascal Meinerzhagen:
ISLPED 2023: International Symposium on Low-Power Electronics and Design. IEEE Des. Test 41(1): 93-94 (2024)- [e1]Pascal Meinerzhagen, Kapil Dev, Jerald Yoo:
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2024, Newport Beach, CA, USA, August 5-7, 2024. ACM 2024, ISBN 979-8-4007-0688-2 [contents] - 2023
- [c23]Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De:
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits 2023: 1-2 - 2020
- [j11]Suyoung Bang, Minki Cho, Pascal Andreas Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits 55(7): 1898-1908 (2020) - [c22]Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang:
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. ITC 2020: 1-10 - [c21]Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen:
Automated Design For Yield Through Defect Tolerance. VTS 2020: 1-6
2010 – 2019
- 2019
- [j10]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [c20]Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC 2019: 1-4 - [c19]Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019: 1-4 - 2018
- [c18]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [j9]Robert Giterman, Adam Teman, Pascal Meinerzhagen:
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1362-1366 (2017) - [c17]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - 2016
- [j8]Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish:
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 222-232 (2016) - [j7]Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 806-817 (2016) - [j6]Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg:
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. 21(4): 59:1-59:25 (2016) - [j5]Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish:
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 358-362 (2016) - [j4]Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish:
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2622-2633 (2016) - [c16]Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg:
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS 2016: 1006-1009 - 2015
- [c15]Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg:
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC 2015: 81-86 - [c14]Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE 2015: 489-494 - [c13]Pascal Andreas Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Peter Burg:
Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. ISCAS 2015: 1426-1429 - 2014
- [j3]Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg:
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 259-263 (2014) - [j2]Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli:
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3155-3164 (2014) - [c12]Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues:
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ESSCIRC 2014: 243-246 - [c11]Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish:
4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS 2014: 2177-2180 - 2013
- [c10]Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici:
FireBird: PowerPC e200 based SoC for high temperature operation. CICC 2013: 1-4 - [c9]Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ESSCIRC 2013: 197-200 - [c8]Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli:
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS 2013: 1-4 - 2012
- [c7]Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC 2012: 321-324 - [c6]Rashid Iqbal, Pascal Andreas Meinerzhagen, Andreas Peter Burg:
Two-port low-power gain-cell storage array: Voltage scaling and retention time. ISCAS 2012: 2469-2472 - [c5]Muhammad Umer Khalid, Pascal Meinerzhagen, Andreas Burg:
Replica bit-line technique for embedded multilevel gain-cell DRAM. NEWCAS 2012: 77-80 - [c4]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. VLSI-SoC (Selected Papers) 2012: 88-106 - [c3]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. VLSI-SoC 2012: 159-164 - 2011
- [j1]Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 173-182 (2011) - [c2]Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Synthesis strategies for sub-VT systems. ECCTD 2011: 552-555 - [c1]Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg:
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. ACM Great Lakes Symposium on VLSI 2011: 343-346
Coauthor Index
aka: Andreas Burg
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last updated on 2024-10-09 21:27 CEST by the dblp team
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