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ORCIDS. M. Yasser Sherazi
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2010 – 2019
- 2015
[j5]Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland
, Viktor Öwall:
Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1863-1872 (2015)- 2014
- [c10]S. M. Yasser Sherazi, Henrik Sjöland, Peter Nilsson:
A digital baseband for low power FSK based receiver in 65 nm CMOS. ICECS 2014: 159-162 - [c9]Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, S. M. Yasser Sherazi:
Supply-voltage down conversion for digital CMOS designs. ICECS 2014: 339-342 - [c8]Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall:
Ultra low power transceivers for wireless sensors and body area networks. ISMICT 2014: 1-5 - 2013
- [j4]S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson:
Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. Microprocess. Microsystems 37(4-5): 494-504 (2013) - [c7]Peter Nilsson, Anusha Gundarapu, S. M. Yasser Sherazi:
Power savings in digital filters for wireless communication. ECCTD 2013: 1-4 - [c6]Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland, Viktor Öwall:
Analog and digital approaches for an energy efficient low complexity channel decoder. ISCAS 2013: 1564-1567 - 2012
- [j3]Henrik Sjöland, John B. Anderson, Carl Bryant, Rohit Chandra, Ove Edfors, Anders J. Johansson, Nafiseh Seyed Mazloum, Reza Meraji, Peter Nilsson, Dejan Radjen, Joachim Neves Rodrigues, S. M. Yasser Sherazi, Viktor Öwall:
A Receiver Architecture for Devices in Wireless Body Area Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1): 82-95 (2012) - [c5]Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC 2012: 321-324 - [c4]S. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Neves Rodrigues:
A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. ICECS 2012: 448-451 - 2011
- [j2]Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 173-182 (2011) - [c3]Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues:
Synthesis strategies for sub-VT systems. ECCTD 2011: 552-555 - [c2]S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues:
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. ISCAS 2011: 837-840 - [c1]Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues:
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. NORCHIP 2011: 1-4 - 2010
- [j1]S. M. Yasser Sherazi, Shahzad Asif, Erik Backenius, Mark Vesterbacka:
Reduction of Substrate Noise in Sub Clock Frequency Range. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(6): 1287-1297 (2010)
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