"Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain."

S. M. Yasser Sherazi et al. (2011)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2011.5937696

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/SheraziNASR11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/SheraziNASR11
S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues:
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. ISCAS 2011: 837-840

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.