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ORCIDVivek De
Vivek K. De
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- affiliation: Intel Labs, Hillsboro, OR, USA
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2020 – today
- 2024
[j86]Vivek De
, Hai Li:
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The "Chips to Systems Conference". IEEE Des. Test 41(6): 95-96 (2024)- [j85]Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew:
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits 59(1): 79-89 (2024) - [j84]Mao Li, Jaehan Park, Sung Justin Kim, Dongkwun Kim, Sanu K. Mathew, Vivek De, Mingoo Seok:
EQZ-LDO: A Secure Digital Low Dropout Regulator Armed With Detection-Driven Protection Against Correlation Power Analysis. IEEE J. Solid State Circuits 59(11): 3806-3815 (2024) - [c166]Suhwan Kim, Harish K. Krishnamurthy, Zakir Ahmed, Nachiket V. Desai, Sheldon Weng, Anne Augustine, Huong T. Do, Jingshu Yu, Phong D. Bach, Xiaosen Liu, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS. ISSCC 2024: 270-272 - [c165]Mao Li, Zhaoqing Wang, Sanu K. Mathew, Vivek De, Mingoo Seok:
16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS. ISSCC 2024: 306-308 - [c164]Sally Amin, Harish Krishnamurthy, Huong Do, Claudio Alvarez, Mike Hill, Kaladhar Radhakrishnan, Vivek De, Sheldon Weng, Krishnan Ravichandran, Jim Tschanz, Wilfred Gomes, Jonathan Douglas:
A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control. VLSI Technology and Circuits 2024: 1-2 - [c163]Vinayak Honkote, Ragh Kuttappa, Jainaveen Sundaram, Satish Yada, Chinnusamy Kalimuthu, Juhi Patil, Richard Lee, Cristan Paulino, Paolo A. Aseron, Trang Nguyen, Amreesh Rao, Dileep Kurian, Mingming Xu, Yan Song, Tanay Karnik, Anuradha Srinivasan, Vivek De:
A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. VLSI Technology and Circuits 2024: 1-2 - [c162]Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew:
A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. VLSI Technology and Circuits 2024: 1-2 - [c161]Jingshu Yu, Xiaosen Liu, Minxiang Gong, Nicolas Butzen, Sheldon Weng, Harish K. Krishnamurthy, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, Waldemer Jim, Christopher Pelto, James W. Tschanz, Vivek De:
A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. VLSI Technology and Circuits 2024: 1-2 - [e4]Vivek De:
Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM 2024, ISBN 979-8-4007-0601-1 [contents] - 2023
- [j83]Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew:
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits 58(4): 1106-1116 (2023) - [c160]Suhwan Kim, Harish K. Krishnamurthy, Sergey Sofer, Sheldon Weng, Shahar Wolf, Ashoke Ravi, Krishnan Ravichandran, Ofir Degani, James W. Tschanz, Vivek De:
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost. ISSCC 2023: 186-187 - [c159]Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew:
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC 2023: 244-245 - [c158]Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De:
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits 2023: 1-2 - [c157]Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew:
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j82]Harry Foster, Rob Oshana, Jörg Henkel, Vivek De:
Report on the Design Automation Conference (DAC 2021). IEEE Des. Test 39(1): 97-99 (2022) - [j81]Archisman Ghosh, Debayan Das, Josef Danial, Vivek De, Santosh Ghosh, Shreyas Sen:
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation. IEEE J. Solid State Circuits 57(1): 167-181 (2022) - [j80]Nachiket V. Desai, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors. IEEE J. Solid State Circuits 57(4): 1090-1099 (2022) - [c156]Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
Improving compute in-memory ECC reliability with successive correction. DAC 2022: 745-750 - [c155]Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De:
Innovations for Intelligent Edge. ESSCIRC 2022: 41-44 - [c154]Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De:
On-Chip High-Resolution Timing Characterization Circuits for Memory IPs. ESSCIRC 2022: 377-380 - [c153]Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew:
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. ISSCC 2022: 1-3 - [c152]Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De:
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. ISSCC 2022: 478-480 - [c151]Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De:
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits 2022: 22-23 - [c150]Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew:
A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits 2022: 138-139 - [c149]Nachiket V. Desai, Harish K. Krishnamurthy, Suhwan Kim, Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation. VLSI Technology and Circuits 2022: 192-193 - 2021
- [j79]Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew:
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE J. Solid State Circuits 56(4): 1141-1151 (2021) - [j78]Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Z. Ahmed, Christopher Schaef, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. IEEE J. Solid State Circuits 56(8): 2402-2415 (2021) - [j77]Ravi R. Iyer, Vivek De, Ramesh Illikkal, David A. Koufaty, Bhushan Chitlur, Andrew Herdrich, Muhammad M. Khellah, Fatih Hamzaoglu, Eric Karl:
Advances in Microprocessor Cache Architectures Over the Last 25 Years. IEEE Micro 41(6): 78-88 (2021) - [j76]Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021) - [j75]Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim:
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2086-2097 (2021) - [c148]Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC 2021: 1-3 - [c147]Nachiket V. Desai, Harish K. Krishnamurthy, Khondker Zakir Ahmed, Sheldon Weng, Suhwan Kim, Xiaosen Liu, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing. ISSCC 2021: 262-264 - [c146]Archisman Ghosh, Debayan Das, Josef Danial, Vivek De, Santosh Ghosh, Shreyas Sen:
36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control. ISSCC 2021: 499-501 - [c145]Khondker Zakir Ahmed, Nachiket V. Desai, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction. VLSI Circuits 2021: 1-2 - [c144]Nachiket V. Desai, Harish K. Krishnamurthy, William J. Lambert, Jingshu Yu, Han Wui Then, Nicolas Butzen, Sheldon Weng, Christopher Schaef, N. Nidhi, Marko Radosavljevic, Johann Rode, Justin Sandford, Kaladhar Radhakrishnan, Krishnan Ravichandran, Bernhard Sell, James W. Tschanz, Vivek De:
A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors. VLSI Circuits 2021: 1-2 - [c143]Suhwan Kim, Harish Krishnamurthy, Sally Amin, Sheldon Weng, Jin Feng, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers. VLSI Circuits 2021: 1-2 - 2020
- [j74]Arvind Singh, Monodeep Kar, Venkata Chaitanya Krishna Chekuri, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. IEEE J. Solid State Circuits 55(2): 478-493 (2020) - [j73]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew:
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55(4): 945-955 (2020) - [j72]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. IEEE J. Solid State Circuits 55(4): 977-987 (2020) - [j71]Suyoung Bang, Minki Cho, Pascal Andreas Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits 55(7): 1898-1908 (2020) - [c142]Harish K. Krishnamurthy, Khondker Zakir Ahmed, Xiaosen Liu, Nachiket V. Desai, Suhwan Kim, Nicolas Butzen, Sally Amin, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Digital Control of Switching and Linear Integrated Voltage Regulators. CICC 2020: 1-4 - [c141]Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC 2020: 380-382 - [c140]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c139]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c138]Zakir Zakir Ahmed, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Christopher Schaef, Nachiket V. Desai, Krishnan Ravichandran, James W. Tschanz, Vivek De:
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering. VLSI Circuits 2020: 1-2 - [c137]Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De:
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits 2020: 1-2 - [c136]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c135]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c134]Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De:
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [c133]Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew:
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. VLSI Circuits 2020: 1-2 - [c132]Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. VLSI Circuits 2020: 1-2 - [c131]Xiaosen Liu, Harish K. Krishnamurthy, Claudia P. Barrera, Jing Han, Rajasekhara M. Narayana Bhatla, Scott Chiu, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. VLSI Circuits 2020: 1-2 - [c130]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De:
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2 - [c129]Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j70]An Chen, Vivek De, Xiaobo Sharon Hu, Michael T. Niemier:
Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies. IEEE Des. Test 36(3): 5-6 (2019) - [j69]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [j68]Arvind Singh, Monodeep Kar, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. IEEE J. Solid State Circuits 54(2): 569-583 (2019) - [j67]Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De:
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54(4): 1074-1085 (2019) - [j66]Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De, Nachiket V. Desai, Harish K. Krishnamurthy, Xiaosen Liu, Khondker Zakir Ahmed, Suhwan Kim, Sheldon Weng, Huong Do, William J. Lambert:
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors. IEEE J. Solid State Circuits 54(12): 3316-3325 (2019) - [c128]Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC 2019: 137-140 - [c127]Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC 2019: 1-4 - [c126]Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019: 1-4 - [c125]Vinayak Honkote, Dileep Kurian, Sriram Muthukumar, Dibyendu Ghosh, Satish Yada, Kartik Jain, Bradley Jackson, Ilya Klotchkov, Mallikarjuna Rao Nimmagadda, Shreela Dattawadkar, Pranjali Deshmukh, Ankit Gupta, Jaykant Timbadiya, Ravi Pali, Karthik Narayanan, Saksham Soni, Saransh Chhabra, Praveen Dhama, N. Sreenivasulu, Jisna Kollikunnel, Sureshbabu Kadavakollu, Vijay Deepak Sivaraj, Paolo A. Aseron, Leonid Azarenkov, Nancy Robinson, Arun Radhakrishnan, Mikhail J. Moiseev, Ganeshram Nandakumar, Akhila Madhukumar, Roman Popov, Kamakhya P. Sahu, Ramesh Peguvandla, Alberto Del Rio Ruiz, Mukesh Bhartiya, Anuradha Srinivasan, Vivek De:
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. ISSCC 2019: 48-50 - [c124]Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging. ISSCC 2019: 146-148 - [c123]Christopher Schaef, Nachiket V. Desai, Harish Krishnamurthy, Sheldon Weng, Huong Do, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation. ISSCC 2019: 154-156 - [c122]Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Z. Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. ISSCC 2019: 234-236 - [c121]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator. ISSCC 2019: 404-406 - [c120]Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits 2019: 32- - [c119]Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits 2019: 50- - [c118]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. VLSI Circuits 2019: 124- - [c117]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234- - [c116]Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits 2019: 238- - 2018
- [j65]Massimo Alioto, Vivek De, Andrea Marongiu:
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 361-368 (2018) - [j64]Massimo Alioto, Vivek De, Andrea Marongiu:
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 653-678 (2018) - [j63]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. IEEE J. Solid State Circuits 53(1): 8-19 (2018) - [j62]Harish Kumar Krishnamurthy, Sheldon Weng, George E. Matthew, Nachiket V. Desai, Ruchir Saraswat, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. IEEE J. Solid State Circuits 53(4): 1038-1048 (2018) - [j61]Monodeep Kar, Arvind Singh, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator. IEEE J. Solid State Circuits 53(8): 2399-2414 (2018) - [c115]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting on-chip power management for side-channel security. DATE 2018: 401-406 - [c114]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - [c113]Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De:
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC 2018: 46-48 - [c112]Vivek De, Dennis Sylvester, James Myers, Jun Deguchi, Shinichiro Shiratake, Ingrid Verbauwhede:
F1: Intelligent energy-efficient systems at the edge of IoT. ISSCC 2018: 502-504 - [c111]Phillip J. Restle, Kostas Doris, Vivek De, Paul Ferguson:
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). ISSCC 2018: 529-531 - [c110]Vivek De:
Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities. NOCS 2018: 1 - [c109]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits 2018: 169-170 - [c108]Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. VLSI Circuits 2018: 195-196 - [i1]Monodeep Kar, Arvind Singh, Sanu Mathew, Santosh Ghosh, Anand Rajan, Vivek De, Raheem A. Beyah, Saibal Mukhopadhyay:
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. CoRR abs/1802.09096 (2018) - 2017
- [j60]Vivek De, Sriram R. Vangal, Ram Krishnamurthy:
Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era. IEEE Des. Test 34(2): 24-30 (2017) - [j59]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J. Hardw. Syst. Secur. 1(4): 340-355 (2017) - [j58]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52(1): 50-63 (2017) - [j57]Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De:
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52(4): 940-949 (2017) - [j56]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De:
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52(4): 961-971 (2017) - [j55]Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS. IEEE J. Solid State Circuits 52(7): 1825-1835 (2017) - [c107]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. ESSCIRC 2017: 51-54 - [c106]Ramnarayanan Muthukaruppan, Tarun Mahajan, Harish Kumar Krishnamurthy, Sumedha Mangal, Am Dhanashekar, Rupak Ghayal, Vivek De:
A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming. ESSCIRC 2017: 275-278 - [c105]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. ISLPED 2017: 1-2 - [c104]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. ISSCC 2017: 142-143 - [c103]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De:
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. ISSCC 2017: 336-337 - [c102]Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst:
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. ISSCC 2017: 506-508 - 2016
- [j54]Vivek De:
Energy-Efficient Computing in Nanoscale CMOS. IEEE Des. Test 33(2): 68-75 (2016) - [j53]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - [j52]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51(1): 117-129 (2016) - [c101]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC 2016: 253-256 - [c100]Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS. ESSCIRC 2016: 453-456 - [c99]Arvind Singh, Monodeep Kar, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines. HOST 2016: 145-148 - [c98]Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
What does ultra low power requirements mean for side-channel secure cryptography? ICCD 2016: 686-689 - [c97]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. ISLPED 2016: 130-135 - [c96]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC 2016: 152-153 - [c95]Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata:
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC 2016: 492-494 - [c94]Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits 2016: 1-2 - [c93]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De:
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c92]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De:
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j51]Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang:
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM J. Emerg. Technol. Comput. Syst. 12(3): 21:1-21:19 (2015) - [j50]Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. IEEE J. Solid State Circuits 50(1): 4-9 (2015) - [j49]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015) - [j48]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(8): 1809-1819 (2015) - [c91]Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. CICC 2015: 1-4 - [c90]Pavan Kumar, Vaibhav A. Vaidya, Harish Krishnamurthy, Stephen T. Kim, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De:
A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. CICC 2015: 1-4 - [c89]Vivek De:
Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs. ICCAD 2015: 159-164 - [c88]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - [c87]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC 2015: 1-3 - 2014
- [j47]Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 49(4): 917-927 (2014) - [c86]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389 - [c85]Vivek De:
Energy efficient computing in nanoscale CMOS: Challenges and opportunities. A-SSCC 2014: 121-124 - [c84]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De:
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. CICC 2014: 1-4 - [c83]Monodeep Kar, Denny Lie, Marilyn Wolf, Vivek De, Saibal Mukhopadhyay:
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. CICC 2014: 1-4 - [c82]Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Borkar, Patrick Yin Chiang:
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. CICC 2014: 1-4 - [c81]Sriram R. Vangal, Shailendra Jain, Vivek De:
A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor. ICICDT 2014: 1-4 - [c80]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - [c79]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC 2014: 276-277 - [c78]Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De:
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC 2014: 278-279 - [c77]Vivek De, Hideyuki Kabuo:
Foreword: Welcome to the 2014 Symposium on VLSI Circuits. VLSIC 2014: 1-2 - [c76]Harish Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De:
A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. VLSIC 2014: 1-2 - 2013
- [j46]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De:
Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test 30(6): 8-17 (2013) - [j45]Vivek De, Hideyuki Kabuo:
Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 48(4): 895-896 (2013) - [j44]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz:
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits 48(4): 907-916 (2013) - [j43]Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De:
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. IEEE J. Solid State Circuits 48(8): 1963-1969 (2013) - [c75]Vivek De:
Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS. ASYNC 2013 - [c74]Vivek De:
Near-threshold voltage design in nanoscale CMOS. DATE 2013: 612 - [c73]Vivek De:
Circuits for resilient systems. FTXS 2013: 11-12 - 2012
- [j42]Makoto Nagata, Vivek De:
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 47(4): 795-796 (2012) - [c72]Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De:
A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. CICC 2012: 1-4 - [c71]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c70]Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar:
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC 2012: 66-68 - [c69]Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 - [c68]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz:
A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC 2012: 94-95 - [c67]Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De:
A fully-digital phase-locked low dropout regulator in 32nm CMOS. VLSIC 2012: 148-149 - 2011
- [j41]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011) - [j40]Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart:
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46(1): 173-183 (2011) - [j39]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - [j38]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46(1): 194-208 (2011) - [j37]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46(4): 797-805 (2011) - [j36]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De:
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2017-2025 (2011) - [c66]Vivek De:
Energy efficient designs with wide dynamic range. CICC 2011: 1 - 2010
- [c65]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c64]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De:
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 - [c63]Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De:
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. CICC 2010: 1-4 - [c62]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 - [c61]Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson:
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109 - [c60]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c59]James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 - [c58]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j35]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 44(1): 49-63 (2009) - [j34]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [j33]Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De:
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44(4): 1199-1208 (2009) - [j32]DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De:
SRAM dynamic stability estimation using MPFP and its applications. Microelectron. J. 40(11): 1523-1530 (2009) - [j31]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 384-394 (2009) - [j30]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2020-2032 (2009) - [c57]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - 2008
- [j29]Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor:
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE J. Solid State Circuits 43(1): 61-68 (2008) - [j28]Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De:
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1904-1910 (2008) - [j27]D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De:
Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1639-1647 (2008) - [c56]Hamed F. Dadgour, Vivek De, Kaustav Banerjee:
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD 2008: 270-277 - [c55]DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De:
Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 - [c54]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - [c53]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC 2008: 402-403 - 2007
- [j26]Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [j25]Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 746-757 (2007) - [j24]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007: 95402:1-95402:12 (2007) - [c52]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - [c51]Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor:
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. ISSCC 2007: 286-603 - [c50]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2006
- [j23]Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) - [j22]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 821-836 (2006) - [j21]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1928-1933 (2006) - [c49]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Reducing the data switching activity of serialized datastreams. ISCAS 2006 - [c48]Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De:
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006 - [c47]Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 - [c46]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432 - [c45]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - [c44]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612 - 2005
- [j20]Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar:
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits 40(4): 838-845 (2005) - [j19]Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra:
Monolithic voltage conversion in low-voltage CMOS technologies. Microelectron. J. 36(9): 863-867 (2005) - [c43]Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling. DAC 2005: 529-534 - [c42]James W. Tschanz, Keith A. Bowman, Vivek De:
Variation-tolerant circuits: circuit solutions and techniques. DAC 2005: 762-763 - [c41]Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De:
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC 2005: 355-358 - [c40]Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge:
Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD 2005: 535-540 - [c39]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 - [c38]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De:
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD 2005: 567-573 - [c37]James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. ISCAS (1) 2005: 9-12 - [c36]Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra:
Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467 - [c35]Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 - [c34]Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED 2005: 26-29 - 2004
- [j18]Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. IEEE J. Solid State Circuits 39(3): 501-510 (2004) - [j17]Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE J. Solid State Circuits 39(9): 1536-1543 (2004) - [j16]Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman:
Low-voltage-swing monolithic dc-dc conversion. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 241-248 (2004) - [c33]Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De:
Design optimizations for microprocessors at low temperature. DAC 2004: 2-5 - [c32]Shekhar Borkar, Tanay Karnik, Vivek De:
Design and reliability challenges in nanometer technologies. DAC 2004: 75 - [c31]Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De:
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED 2004: 263-268 - [c30]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521 - 2003
- [j15]Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid State Circuits 38(5): 696-701 (2003) - [j14]James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De:
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. IEEE J. Solid State Circuits 38(5): 826-829 (2003) - [j13]Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De:
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38(5): 839-842 (2003) - [j12]James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits 38(11): 1838-1845 (2003) - [j11]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 514-522 (2003) - [j10]Vivek De, Luca Benini:
Guest editorial. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 753-754 (2003) - [j9]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 863-870 (2003) - [c29]Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC 2003: 617-620 - [c28]Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 - [c27]Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De:
Compiler Support for Reducing Leakage Energy Consumption. DATE 2003: 11146-11147 - [c26]Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson:
Bitline leakage equalization for sub-100nm caches. ESSCIRC 2003: 401-404 - [c25]Stephen Tang, Siva G. Narendra, Vivek De:
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. ISLPED 2003: 199-204 - [c24]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279- - 2002
- [j8]Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. 19(5): 36-43 (2002) - [j7]James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Vivek De:
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid State Circuits 37(11): 1396-1402 (2002) - [j6]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002) - [j5]Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 91-95 (2002) - [c23]Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar:
High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC 2002: 125-128 - [c22]George Sery, Shekhar Borkar, Vivek De:
Life is CMOS: why chase the life after? DAC 2002: 78-83 - [c21]Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 - [c20]Tanay Karnik, Shekhar Borkar, Vivek De:
Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 - [c19]Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan:
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED 2002: 19-23 - [c18]Vivek De:
Leakage-tolerant design techniques for high performance processors. ISPD 2002: 28-28 - [c17]Ron Wilson, Siva G. Narendra, Vivek De:
Evening Panel Discussion: Process Variation: Is It Too Much to Handle? ISQED 2002: 213- - [c16]Jaume Segura, Vivek De, Ali Keshavarzi:
Challenges in Nanometric Technology Scaling: Trends and Projections. VTS 2002: 447-448 - [e3]Kanad Ghose, Patrick H. Madden, Vivek De, Peter M. Kogge:
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002. ACM 2002, ISBN 1-58113-462-2 [contents] - [e2]Vivek De, Mary Jane Irwin, Ingrid Verbauwhede, Christian Piguet:
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002. ACM 2002, ISBN 1-58113-475-4 [contents] - 2001
- [c15]James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 - [c14]Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar:
Scaling of stack effect and its application for leakage reduction. ISLPED 2001: 195-200 - [c13]Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De:
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED 2001: 207-212 - [e1]Enrico Macii, Vivek De, Mary Jane Irwin:
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001. ACM 2001, ISBN 1-58113-371-5 [contents] - 2000
- [c12]Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De:
Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243 - [c11]Vivek De, Shekhar Borkar:
Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI 2000: 1-6 - [c10]Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059 - [c9]Liqiong Wei, Kaushik Roy, Vivek De:
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design 2000: 24-29
1990 – 1999
- 1999
- [j4]Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De:
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 16-24 (1999) - [c8]Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De:
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435 - [c7]Vivek De, Shekhar Borkar:
Technology and design challenges for low power and high performance. ISLPED 1999: 163-168 - [c6]Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 - 1998
- [j3]P. Pant, Vivek K. De, A. Chatterjee:
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 538-545 (1998) - [c5]Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De:
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494 - 1997
- [j2]Xinghai Tang, Vivek De, James D. Meindl:
Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 369-376 (1997) - [c4]Pankaj Pant, Vivek De, Abhijit Chatterjee:
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. DAC 1997: 403-408 - 1996
- [c3]Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl:
Circuit techniques for low-power CMOS GSI. ISLPED 1996: 193-196 - [c2]Xinghai Tang, Vivek De, James D. Meindl:
Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED 1996: 233-236 - [c1]Vivek De, James D. Meindl:
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED 1996: 371-375 - 1994
- [j1]Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl:
Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE J. Solid State Circuits 29(2): 122-125 (1994)
Coauthor Index
Khondker Zakir Ahmed
aka: Khondker Z. Ahmed
aka: Khondker Z. Ahmed
Shekhar Borkar
aka: Shekhar Y. Borkar
aka: Shekhar Y. Borkar
Steven Hsu
aka: Steven K. Hsu
aka: Steven K. Hsu
[c158] [j77] [j75] [j71] [c141] [c137] [c134] [c130] [j69] [c127] [c126] [c114] [j58] [j53] [c96] [c94] [c91] [c88] [j47] [c80] [c71] [c69] [j41] [j38] [j37] [j36] [c65] [c64] [c63] [c62] [c59] [c58] [j34] [j33] [j32] [j31] [j30] [j28] [j27] [c55] [c54] [j26] [j25] [j24] [j22] [j21] [c49] [c48] [c47] [c46] [c45] [c43] [c39] [c35] [j13]
Ram Krishnamurthy 0001
aka: Ram K. Krishnamurthy
aka: Ram K. Krishnamurthy
Jaydeep P. Kulkarni
aka: Jaydeep Kulkarni
aka: Jaydeep Kulkarni
Andres Malavasi
aka: Andres F. Malavasi
aka: Andres F. Malavasi
Sanu Mathew
aka: Sanu K. Mathew
aka: Sanu K. Mathew
James W. Tschanz
aka: Jim Tschanz
aka: Jim Tschanz
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