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Journal Articles
- 2024
[j7]Raghavan Kumar
, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew:
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits 59(1): 79-89 (2024)- 2023
- [j6]Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew:
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits 58(4): 1106-1116 (2023) - 2022
- [j5]Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto:
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. IEEE J. Solid State Circuits 57(1): 153-166 (2022) - 2021
- [j4]Sachin Taneja, Massimo Alioto:
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. IEEE J. Solid State Circuits 56(7): 2182-2192 (2021) - [j3]Sachin Taneja, Massimo Alioto:
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core. IEEE J. Solid State Circuits 56(10): 3049-3061 (2021) - 2019
- [j2]Muhammad Naveed Aman, Sachin Taneja, Biplab Sikdar, Kee Chaing Chua, Massimo Alioto:
Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff. IEEE Internet Things J. 6(2): 2843-2859 (2019) - 2018
- [j1]Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto:
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid State Circuits 53(10): 2828-2839 (2018)
Conference and Workshop Papers
- 2024
- [c15]Minxuan Zhou, Yujin Nam, Xuan Wang, Youhak Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing:
UFC: A Unified Accelerator for Fully Homomorphic Encryption. MICRO 2024: 352-365 - [c14]Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew:
A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c13]Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew:
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC 2023: 244-245 - [c12]Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto:
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. VLSI Technology and Circuits 2023: 1-2 - [c11]Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits 2023: 1-2 - [c10]Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew:
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c9]Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew:
A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits 2022: 138-139 - 2021
- [c8]Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSCIRC 2021: 127-130 - [c7]Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto:
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. ESSDERC 2021: 127-130 - [c6]Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto:
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. ISSCC 2021: 498-500 - 2020
- [c5]Sachin Taneja, Massimo Alioto:
Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. ISCAS 2020: 1-5 - 2019
- [c4]Massimo Alioto, Sachin Taneja:
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper). CICC 2019: 1-8 - [c3]Sachin Taneja, Massimo Alioto:
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion. ESSCIRC 2019: 61-64 - 2017
- [c2]Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto:
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. A-SSCC 2017: 301-304 - 2015
- [c1]Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain:
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. SoCC 2015: 304-309
Informal and Other Publications
- 2018
- [i1]Sachin Taneja, Massimo Alioto:
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems. CoRR abs/1811.08507 (2018)
Coauthor Index
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