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2020 – today
- 2023
[c9]Xiaotian Zhao
, Yimin Gao, Vaibhav Verma, Ruge Xu, Mircea Stan, Xinfei Guo:
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units. ACM Great Lakes Symposium on VLSI 2023: 467-471- [c8]Yimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma, Xinfei Guo, Mircea Stan:
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores. SOCC 2023: 1-6 - 2022
- [j3]Vaibhav Verma, Tommy Tracy II, Mircea R. Stan:
EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT. Sustain. Comput. Informatics Syst. 35: 100742 (2022) - 2021
- [c7]Mohammad Nazmus Sakib, Rahul Sreekumar, Vaibhav Verma, Tommy Tracy II, Mircea R. Stan:
ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge. WF-IoT 2021: 704-709 - 2020
- [c6]Vaibhav Verma, Fiza Akhtar, Anuj Grover:
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j2]Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron:
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. IEEE Comput. Archit. Lett. 18(2): 87-90 (2019) - [c5]Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron:
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing. MICRO 2019: 87-99 - 2018
- [c4]Yunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, Xuan Zhang:
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. DAC 2018: 41:1-41:6 - [c3]Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea R. Stan:
When "things" get older: Exploring circuit aging in IoT applications. ISQED 2018: 296-301 - 2017
- [j1]Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, Mircea R. Stan:
Back to the Future: Digital Circuit Design in the FinFET Era. J. Low Power Electron. 13(3): 338-355 (2017) - 2015
- [c2]Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain:
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. SoCC 2015: 304-309 - 2014
- [c1]Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja:
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. VLSID 2014: 150-155
Coauthor Index
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