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ORCIDISQED 2003: San Jose, California, USA
- 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA. IEEE Computer Society 2003, ISBN 0-7695-1881-8
Design for Yield Optimization and Test
- Adit D. Singh:
Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". 7 - Israel Koren, Julie D. Segal:
Optimizing the Yield of VLSI Circuits. 7
Design for Manufacturing and Yield
- Zoran Stamenkovic:
Testing and Yield of Integrated Circuits. 8 - Duane S. Boning:
Test Structures for Circuit Yield Assessment and Modeling. 8 - Enrico Malavasi:
Design Based Yield Improvements (DBYI). 9 - Giuseppe Crisenza:
Yield in flash memory: Methodology, modeling and design issues. 9
IC and Package Co-Design
- Marco Casale-Rossi:
Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification. 10 - Rich Evans:
A Package Design Perspective, "It will be BGA and Flip-Chip". 11 - Anna Fontanelli:
An EDA Perspective, "We Need it Yesterday! 11 - Kevin Rinebold:
An EDA Perspective, "Let's do it Concurrently! 11
Design for Reliability
- Mohsen Alavi:
Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design Considerations. 12 - Ken Tseng:
Noise Analysis for 0.13um and Beyond. 12 - Lifeng Wu:
NBTI/HCI Modeling and Full-Chip Analysis in Design Environment. 13-14 - Steven Ohr:
Is Quality a Design Constraint for Sub 100nm Designs? 15-17
Plenary Session I
- Platform Leadership in the Ambient Intelligence Era. 21-22
- Quality SoC Design and Implementation for Real Manufacturability. 23-24
- Quality Challenges of the Nanometer Design Realm. 25-
Reducing Leakage Currents in VLSI Circuits
- Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. 49-54 - Geun Rae Cho, Tom Chen:
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. 55-60 - Rafik S. Guindi, Farid N. Najm:
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. 61-65
SoC Methodology
- Bijan Alizadeh, Mohammad Reza Kakoee:
Using Integer Equations for High Level Formal Verification Property Checking. 69-74 - Gary Feierbach, Vijay Gupta:
True Coverage: A Goal of Verification. 75-78 - Gustavo Marrero Callicó, Antonio Núñez
, Rafael Peset Llopis, Ramanathan Sethuraman:
Low-Cost and Real-Time Super-Resolution over a Video Encoder IP. 79-84 - Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron:
LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction. 85-89
Testing of SoCs
- Sandeep Koranne:
Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers. 93-98 - Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy:
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. 99-104 - Chunsheng Liu, Krishnendu Chakrabarty:
Compact Dictionaries for Fault Diagnosis in BIST. 105-110 - Chien-In Henry Chen, Kiran George:
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. 111-116
Design for Manufacturability and Quality
- F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh:
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. 119-124 - Qi-De Qian, Sheldon X.-D. Tan:
Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis. 125-130 - Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto:
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains. 131-137 - M. C. Scott, M. O. Peralta, Jo Dale Carothers:
System and Framework for QA of Process Design Kits. 138-143 - Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Sridhar Subramaniam, Hem Hingarh:
The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange. 144-149
Design Considerations in Advanced Technology
- Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim:
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. 153-158 - Won Namgoong, Jongrit Lerdworatawee:
Revisiting the Noise Figure Design Metric for Digital Communication Receiver. 159-162 - N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell:
Benchmarks for Interconnect Parasitic Resistance and Capacitance. 163-168
Interconnect and Substrate Noise
- Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction. 171-176 - Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Noise-Aware Driver Modeling for Nanometer Technology. 177-182 - Tom Chen, Amjad Hajjar:
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. 183-188 - Chung-Kuan Tsai, Malgorzata Marek-Sadowska:
Modeling Crosstalk Induced Delay. 189-194 - Hai Lan, Zhiping Yu, Robert W. Dutton:
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. 195-200
Impact of New Standards for Design Data Modeling and Manufacturing Interface
- Terry Blanchard:
Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer. 203-207 - Andrew B. Kahng, Igor L. Markov:
Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. 208-213 - D. R. Cottrell, T. J. Grebinski:
Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing. 214-219
Package-Design Interface Challenges
- Peter C. Salmon:
Advanced Module Packaging Method. 223-228 - Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai:
Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform. 229-234 - Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim, Madhavan Swaminathan:
Modeling and Analysis of Power Distribution Networks for Gigabit Applications. 235-240 - Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang:
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. 241-246
IC and Package Co-Design: Challenge or Dream?
- Addressing the IC Designer's Needs: Integrated Design Software for Faster, More Economical Chip Design. 253-254
- Closing the Gap between ASIC and Full Custom: A Path to Quality Design. 255-256
- A VLSI System Perspective for Microprocessors Beyond 90nm. 257-
Power Analysis and Low Power Design
- Soroush Abbaspour, Massoud Pedram, Payam Heydari:
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. 261-266 - Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang:
Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs. 267-272 - Puneet Gupta, Andrew B. Kahng:
Quantifying Error in Dynamic Power Estimation of CMOS Circuits. 273-278 - Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. 279-
Topics in Device and Interconnect Modeling
- Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester:
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. 287-292 - Payam Heydari:
Design and Analysis of Low-Voltage Current-Mode Logic Buffers. 293-298 - Makram M. Mansour, Amit Mehrotra:
Reduced-Order Modeling Based on PRONY's and SHANK's Methods via the Bilinear Transformation. 299-304
Techniques for High-Speed Circuits and Module Generation
- Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim:
A Novel Clocking Strategy for Dynamic Circuits. 307-312 - Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco B. Litovski:
Procedural Analog Design (PAD) Tool. 313-318 - Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra:
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs. 319-324
Timing and Noise Issues in Physical Design
- Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. 327-332 - Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing Inter-Clock Coupling Jitter. 333-338 - Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. 339-343 - Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong:
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. 344-347 - Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura:
PDL: A New Physical Synthesis Methodology. 348-354
Reliabililty Analysis
- Colin C. McAndrew:
Statistical Modeling for Circuit Simulation. 357-362 - Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng:
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. 363-368 - Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Coupled Simulation of Circuit and Piezoelectric Laminates. 369-372 - Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong:
Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling. 373-376 - Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta:
Static Electromigration Analysis for Signal Interconnects. 377-382
Panel Discussion: Hidden Quality, Crouching Customer-How Much Does the Quality of EDA Tools Impact Electronic Design?
- Tets Maniwa:
Hidden Quality, Crouching Customer - How Much Does the Quality of EDA Tools Impact Electronic Design? 383-385
Interconnect Parasitic Effects
- S. Simon Wong, C. Patrick Yue, Richard Chang, So-Young Kim, Bendik Kleveland, Frank O'Mahony:
On-Chip Interconnect Inductance - Friend or Foe (Invited). 389-394 - Takashi Sato, Hiroo Masuda:
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. 395-400 - Soyoung Kim, Yehia Massoud, S. Simon Wong:
On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond. 401-404 - Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright:
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. 405-409 - Li Yang, J. S. Yuan:
Analyzing Internal-Switching Induced Simultaneous Switching Noise. 410-415
Design and Measurement Issues in Testing
- Maria K. Michael, Spyros Tragoudas:
Generation of Hazard Identification Functions. 419-424 - Petros Drineas, Yiorgos Makris:
Concurrent Fault Detection in Random Combinational Logic. 425-430 - Daniela De Venuto, Michael J. Ohletz, Bruno Riccò:
Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes. 431-437 - Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang:
On Structural vs. Functional Testing for Delay Faults. 438-441 - Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
An Embedded IDDQ Testing Architecture and Technique. 442-445
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