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2020 – today
- 2024
[c33]Jihwan Kim, Ariel Cohen, Mike Peng Li, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony:
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. CICC 2024: 1-8- 2023
- [j12]Ahmad Khairi, Yoel Krupnik
, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Sabag, Vitali Rahinski, Idan Lotan, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky Grafi, Udi Virobnik, Dror Lazar, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Frank O'Mahony, Ariel Cohen:
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. IEEE J. Solid State Circuits 58(1): 8-18 (2023) - 2022
- [j11]Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyasaachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yoav Segal, Yongping Fan, Peng Li, Frank O'Mahony:
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 57(1): 6-20 (2022) - [c32]Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri:
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. ISSCC 2022: 42-44 - 2021
- [c31]Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, Frank O'Mahony:
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. ISSCC 2021: 126-128 - [c30]Shiva Kiran, Ajay Balankutty, Yutao Liu, Rajeev Dokania, Hariprasath Venkataraman, Priya Wali, Stephen Kim, Yoel Krupnik, Ariel Cohen, Frank O'Mahony:
A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c29]Wilfred Gomes, Sanjeev Khushu, Doug B. Ingerly, Patrick N. Stover, Nasirul I. Chowdhury, Frank O'Mahony, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Lei Jiang, Surya Prekke, Biswajit Patra, Pavel V. Rott, Rajesh Kumar:
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. ISSCC 2020: 144-146
2010 – 2019
- 2019
- [j10]Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 54(1): 29-42 (2019) - 2018
- [c28]Mounir Meghelli, Hyeon-Min Bae, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. ISSCC 2018: 100-101 - [c27]Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. ISSCC 2018: 102-104 - [c26]Azita Emami, Andrew K. Joy, Frank O'Mahony:
Session 16 overview: Advanced optical and wireline techniques: Wireline subcommittee. ISSCC 2018: 262-263 - [c25]Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony:
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. ISSCC 2018: 388-389 - 2017
- [c24]Simone Erba, Takayuki Shibasaki, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline. ISSCC 2017: 108-109 - [c23]Samuel Palermo, Hideyuki Nosaka, Frank O'Mahony:
Session 29 overview: Optical- and electrical-link innovations. ISSCC 2017: 480-481 - 2016
- [j9]Ishita Mukhopadhyay, Mustansir Yunus Mukadam, Rajendran Narayanan, Frank O'Mahony, Alyssa B. Apsel:
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1050-1058 (2016) - [c22]Frank O'Mahony, Simone Erba:
Session 23 overview: Electrical and optical link innovations. ISSCC 2016: 396-397 - 2015
- [j8]Tzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements. IEEE J. Solid State Circuits 50(7): 1711-1721 (2015) - [c21]Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr:
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. ISSCC 2015: 1-2 - [c20]Rajeev K. Dokania, Alexandra M. Kern, Mike He, Adam C. Faust, Richard Tseng, Skyler Weaver, Kai Yu, Christiaan Bil, Tao Liang, Frank O'Mahony:
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. ISSCC 2015: 1-3 - [c19]Jack Kenney, Frank O'Mahony:
EP3: Innovating on the tapeout treadmill. ISSCC 2015: 1 - [c18]Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. ISSCC 2015: 1-3 - 2014
- [c17]Tzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
An on-die all-digital power supply noise analyzer with enhanced spectrum measurements. ESSCIRC 2014: 251-254 - [c16]Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon:
F6: Energy-efficient I/O design for next-generation systems. ISSCC 2014: 520-521 - [c15]Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. VLSIC 2014: 1-2 - 2013
- [j7]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. IEEE J. Solid State Circuits 48(12): 3229-3242 (2013) - [c14]Sudip Shekhar, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
Design considerations for low-power receiver front-end in high-speed data links. CICC 2013: 1-8 - [c13]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. ISSCC 2013: 402-403 - 2012
- [c12]Mozhgan Mansuri, Bryan Casper, Frank O'Mahony:
An on-die all-digital delay measurement circuit with 250fs accuracy. VLSIC 2012: 98-99 - 2010
- [j6]Kangmin Hu, Tao Jiang, Jingguang Wang, Frank O'Mahony, Patrick Yin Chiang:
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. IEEE J. Solid State Circuits 45(4): 899-908 (2010) - [j5]Frank O'Mahony, James E. Jaussi, Joseph T. Kennedy, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. IEEE J. Solid State Circuits 45(12): 2828-2837 (2010) - [c11]Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony:
Varactor-based signal restoration for near-speed-of-light surfing global interconnect. CICC 2010: 1-4 - [c10]Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. ISSCC 2010: 156-157 - [c9]Ganesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Bryan Casper:
A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS. ISSCC 2010: 372-373
2000 – 2009
- 2009
- [j4]Bryan Casper, Frank O'Mahony:
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links - A Tutorial. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 17-39 (2009) - [j3]Sudip Shekhar, Ganesh Balamurugan, David J. Allstot, Mozhgan Mansuri, James E. Jaussi, Randy Mooney, Joseph T. Kennedy, Bryan Casper, Frank O'Mahony:
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1818-1829 (2009) - [c8]Dong Hun Shin, Ji-Eun Jang, Frank O'Mahony, C. Patrick Yue:
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. CICC 2009: 117-120 - 2008
- [j2]Ganesh Balamurugan, Joseph T. Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney:
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. IEEE J. Solid State Circuits 43(4): 1010-1019 (2008) - [c7]Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper:
Strong injection locking of low-Q LC oscillators. CICC 2008: 699-702 - [c6]Frank O'Mahony, Sudip Shekhar, Mozhgan Mansuri, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Bryan Casper, David J. Allstot, Randy Mooney:
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. ISSCC 2008: 452-453 - 2006
- [c5]Bryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joseph T. Kennedy, E. Yeung, Randy Mooney:
A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. ISSCC 2006: 263-272 - [c4]Bryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joe Kennedy, Randy Mooney:
A 20Gb/s Embedded Clock Transceiver in 90nm CMOS. ISSCC 2006: 1334-1343 - 2005
- [c3]Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue:
A low-power, 20-Gb/s continuous-time adaptive passive equalizer. ISCAS (2) 2005: 920-923 - 2003
- [j1]Frank O'Mahony, C. Patrick Yue, Mark A. Horowitz, S. Simon Wong:
A 10-GHz global clock distribution using coupled standing-wave oscillators. IEEE J. Solid State Circuits 38(11): 1813-1820 (2003) - [c2]Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong:
Design of a 10GHz clock distribution network using coupled standing-wave oscillators. DAC 2003: 682-687 - [c1]S. Simon Wong, C. Patrick Yue, Richard Chang, So-Young Kim, Bendik Kleveland, Frank O'Mahony:
On-Chip Interconnect Inductance - Friend or Foe (Invited). ISQED 2003: 389-394
Coauthor Index
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last updated on 2024-06-04 21:31 CEST by the dblp team
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