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2020 – today
- 2024
[j118]Hyunjin Kim
, ChangHun Park, Inho Park, Taehyeong Park, Seungwoo Park, Chulwoo Kim:
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. IEEE J. Solid State Circuits 59(2): 551-562 (2024)- [j117]Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits 59(4): 1261-1270 (2024) - [j116]Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim:
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59(6): 1835-1846 (2024) - [j115]Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim:
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits 59(8): 2518-2528 (2024) - [j114]Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim:
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 59(10): 3432-3443 (2024) - [j113]Hyunjin Kim, Taehyeong Park, Inho Park, ChangHun Park, Seokjin Kim, Seokhee Han, Junwon Jeong, Chulwoo Kim:
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications. IEEE J. Solid State Circuits 59(10): 3444-3456 (2024) - [j112]Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seonbeen Lee, Chulwoo Kim:
A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. IEEE J. Solid State Circuits 59(11): 3730-3740 (2024) - [j111]Taehyeong Park, Hyunjin Kim, Mingi Jeong, Inho Park, Chulwoo Kim:
A Fully Integrated Dual-Output Continuously Scalable-Conversion-Ratio SC Converter for Battery-Powered IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3463-3475 (2024) - [j110]Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3328-3332 (2024) - [j109]Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim:
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4096-4100 (2024) - [j108]Yohan Choi, Woojin Lee, Sooho Park, Changjoo Kim, Hyundo Jung, Chulwoo Kim:
A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4141-4145 (2024) - [j107]Junyoung Maeng, Junwon Jeong, Inho Park, Minseob Shim, Chulwoo Kim:
A Time-Based Direct MPPT Technique for Low-Power Photovoltaic Energy Harvesting. IEEE Trans. Ind. Electron. 71(5): 5375-5380 (2024) - 2023
- [j106]Inho Park, Jinwoo Jeon, Hyunjin Kim, Taehyeong Park, Junwon Jeong, Chulwoo Kim:
A Thermoelectric Energy-Harvesting Interface With Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method. IEEE J. Solid State Circuits 58(6): 1706-1718 (2023) - [j105]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58(7): 2005-2015 (2023) - [j104]Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim:
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58(8): 2314-2325 (2023) - [j103]Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1907-1916 (2023) - [j102]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim:
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2734-2743 (2023) - [j101]Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim:
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 101-105 (2023) - [j100]Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim:
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 904-908 (2023) - [c77]Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim:
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC 2023: 118-119 - 2022
- [j99]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. IEEE J. Solid State Circuits 57(2): 562-572 (2022) - [j98]Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim:
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. IEEE J. Solid State Circuits 57(5): 1492-1503 (2022) - [j97]Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, Chulwoo Kim:
An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 57(9): 2778-2790 (2022) - [j96]Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Chulwoo Kim:
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3416-3427 (2022) - [j95]Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim:
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 404-408 (2022) - [j94]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 794-798 (2022) - [j93]Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Chulwoo Kim:
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2737-2741 (2022) - [c76]Jong-Min Kim, Ju-Hyung Lee, Yeongrok Lee, Hong-Seol Cha, Hyunsu Park, Jincheol Sim, Chulwoo Kim, Young-Chai Ko:
Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance. INFOCOM Workshops 2022: 1-2 - [c75]Jeewan Lee, Yoonjae Choi, Chulwoo Kim:
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers. ISCAS 2022: 2177-2181 - [c74]Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC 2022: 1-3 - [c73]Hyunjin Kim, Taehyeong Park, Chulwoo Kim:
A 97.9% Peak Efficiency 9 V Output Three-Switch Hybrid Buck-Boost Power Stage Using 5 V CMOS. MWSCAS 2022: 1-4 - [c72]Hyunjin Kim, ChangHun Park, Chulwoo Kim:
An Output-Boosted 3-ratio Switched-Capacitor DC-DC Converter with 0.5-to-1.8 V Output Voltage Range for Low-Power IoT Applications. MWSCAS 2022: 1-4 - 2021
- [j92]Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim:
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9: 118907-118918 (2021) - [j91]Junyoung Maeng, Inho Park, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits 56(2): 541-553 (2021) - [j90]Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim:
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits 56(2): 581-590 (2021) - [j89]Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Dongju Lim, Chulwoo Kim:
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode. IEEE J. Solid State Circuits 56(3): 961-971 (2021) - [j88]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim:
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021) - [j87]Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Yohan Choi, Chulwoo Kim:
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme. IEEE J. Solid State Circuits 56(9): 2724-2735 (2021) - [j86]Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soonsung Ahn, Sooho Park, Chulwoo Kim:
A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3242-3253 (2021) - [j85]Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim:
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3189-3193 (2021) - [j84]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1567-1574 (2021) - [c71]Jinwoo Jeon, Junyoung Maeng, Inho Park, Hyunjin Kim, Chulwoo Kim:
A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode. ISCAS 2021: 1-5 - [c70]Inho Park, Jinseok Oh, Chulwoo Kim:
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique. ISCAS 2021: 1-4 - [c69]Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim:
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. ISCAS 2021: 1-4 - 2020
- [j83]Jaehun Jun, Sangsu Lee, Chulwoo Kim:
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system. IET Circuits Devices Syst. 14(2): 155-158 (2020) - [j82]Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications. IEEE J. Solid State Circuits 55(5): 1324-1336 (2020) - [j81]Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, Yunsoo Park, Chulwoo Kim:
A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance. IEEE J. Solid State Circuits 55(6): 1624-1636 (2020) - [j80]Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim:
An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier. IEEE J. Solid State Circuits 55(9): 2468-2477 (2020) - [j79]Jaegeun Song, Jaehun Jun, Chulwoo Kim:
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1184-1188 (2020) - [j78]Youngbog Yoon, Chulwoo Kim:
An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1775-1779 (2020) - [j77]Youngbog Yoon, Hyunsu Park, Chulwoo Kim:
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. IEEE Trans. Circuits Syst. 67-II(11): 2342-2346 (2020) - [c68]Soonsung Ahn, Jaegeun Song, Chaegang Lim, Yohan Choi, Sooho Park, Yunsoo Park, Chulwoo Kim:
A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. ISOCC 2020: 1-2
2010 – 2019
- 2019
- [j76]Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54(2): 463-475 (2019) - [j75]Junwon Jeong, Seokhyeon Jeong, Dennis Sylvester, David T. Blaauw, Chulwoo Kim:
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries. IEEE J. Solid State Circuits 54(2): 524-537 (2019) - [j74]Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 192-196 (2019) - [j73]Junyoung Song, Yongtae Kim, Chulwoo Kim:
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1982-1986 (2019) - [j72]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c67]Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim:
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC 2019: 382-384 - [c66]Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency. VLSI Circuits 2019: 326- - 2018
- [j71]Wonsup Lee, Baekhee Lee, Xiaopeng Yang, Hayoung Jung, Ilgeun Bok, Chulwoo Kim, Ochae Kwon, Heecheon You:
A 3D anthropometric sizing analysis system based on North American CAESAR 3D scan data for design of head wearable products. Comput. Ind. Eng. 117: 121-130 (2018) - [j70]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 331-342 (2018) - [j69]Jaehun Jun, Jaegeun Song, Chulwoo Kim:
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1567-1580 (2018) - [j68]Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim:
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 789-793 (2018) - [j67]Jaehun Jun, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1509-1513 (2018) - [c65]Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David T. Blaauw:
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries. ASP-DAC 2018: 281-282 - [c64]Yeonho Lee, Yoonjae Choi, Chulwoo Kim:
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. ASP-DAC 2018: 287-288 - [c63]Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung:
Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. ASP-DAC 2018: 295-296 - [c62]Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage. ISSCC 2018: 146-148 - 2017
- [j66]Young-Jae Min, Chan-Hui Jeong, Junil Moon, Youngsun Han, Soo-Won Kim, Chulwoo Kim:
A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system. IEICE Electron. Express 14(13): 20170461 (2017) - [j65]Sang-Geun Bae, Yongtae Kim, Yunsoo Park, Chulwoo Kim:
3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop. IEEE J. Solid State Circuits 52(2): 605-610 (2017) - [j64]Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung:
Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J. Solid State Circuits 52(4): 1077-1090 (2017) - [j63]Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim:
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 650-654 (2017) - [j62]Sang-Geun Bae, Gyungmin Kim, Chulwoo Kim:
A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1132-1136 (2017) - [j61]Jungtaek You, Junyoung Song, Chulwoo Kim:
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1207-1211 (2017) - [j60]Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2691-2702 (2017) - [j59]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j58]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 344-353 (2017) - [c61]Chulwoo Kim, Sung-Hyuk Cha, Yoo Jung An, Ned Wilson:
On ROC Curve Analysis of Artificial Neural Network Classifiers. FLAIRS 2017: 318-322 - [c60]Sangsu Lee, Jaehun Jun, Chulwoo Kim:
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. ISOCC 2017: 180-181 - [c59]Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim:
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC 2017: 490-491 - 2016
- [j57]Edith Beigné, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe:
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51(1): 3-7 (2016) - [j56]Yunsoo Park, Jintae Kim, Chulwoo Kim:
A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1889-1897 (2016) - [j55]Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1092-1103 (2016) - [j54]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2768-2777 (2016) - [c58]Byung Gun Joung, Yangho Seo, Chulwoo Kim:
A digital low-dropout(DLDO) regulator with 14dB power supply rejection enhancement. ISOCC 2016: 353-354 - [c57]Chulwoo Kim, Martin Brox:
Session 18 overview: High-bandwidth DRAM. ISSCC 2016: 312-313 - [c56]Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim:
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits 2016: 1-2 - [c55]Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung:
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. VLSI Circuits 2016: 1-2 - 2015
- [j53]Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim:
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. IEEE J. Solid State Circuits 50(2): 414-425 (2015) - [j52]Minseob Shim, Jungmoon Kim, Junwon Jeong, Sejin Park, Chulwoo Kim:
Self-Powered 30 µW to 10 mW Piezoelectric Energy Harvesting System With 9.09 ms/V Maximum Power Point Tracking Time. IEEE J. Solid State Circuits 50(10): 2367-2379 (2015) - [j51]Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim:
D2ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing. Microprocess. Microsystems 39(8): 767-781 (2015) - [j50]Hokyu Lee, Sejin Park, Chaegang Lim, Chulwoo Kim:
A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter. IEEE Trans. Circuits Syst. II Express Briefs 62-II(4): 357-361 (2015) - [j49]Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, Chulwoo Kim:
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2371-2383 (2015) - [c54]Chulwoo Kim:
Circuit design techniques for multimedia wireline communications. ASICON 2015: 1-4 - [c53]Jonathan Chang, Leland Chang, Antoine Dupret, Chulwoo Kim, Fatih Hamzaoglu, Takefumi Yoshikawa:
F2: Memory trends: From big data to wearable devices. ISSCC 2015: 1-2 - [c52]Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim:
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC 2015: 1-3 - 2014
- [b2]Chulwoo Kim, Hyun-Woo Lee, Junyoung Song:
High-Bandwidth Memory Interface. Springer Briefs in Electrical and Computer Engineering, Springer 2014, ISBN 978-3-319-02380-9, pp. i-viii, 1-88 - [j48]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 865-869 (2014) - [j47]Hyun-Woo Lee, Chulwoo Kim:
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 701-711 (2014) - [j46]Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim:
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2156-2163 (2014) - [c51]Jungmoon Kim, Chulwoo Kim:
A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator. ASP-DAC 2014: 33-34 - [c50]Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim:
A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications. ASP-DAC 2014: 35-36 - [c49]Heejun Kim, Jungmoon Kim, Minseob Shim, Junwon Jung, Sejin Park, Chulwoo Kim:
A digitally controlled DC-DC buck converter with bang-bang control. ICEIC 2014: 1-2 - [c48]Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim:
23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement. ISSCC 2014: 394-395 - [c47]Minseob Shim, Jungmoon Kim, Junwon Jung, Chulwoo Kim:
23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time. ISSCC 2014: 406-407 - [c46]Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong:
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC 2014: 434-435 - [c45]Frank O'Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon:
F6: Energy-efficient I/O design for next-generation systems. ISSCC 2014: 520-521 - 2013
- [j45]Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim:
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. IEEE J. Solid State Circuits 48(3): 711-723 (2013) - [j44]Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim:
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 268-278 (2013) - [j43]Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim:
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 303-313 (2013) - [j42]Hoon Ki Kim, Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Chulwoo Kim, Soo-Won Kim:
A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter. IEEE Trans. Circuits Syst. II Express Briefs 60-II(6): 331-335 (2013) - [j41]Sewook Hwang, Jabeom Koo, Kisoo Kim, Hokyu Lee, Chulwoo Kim:
A 0.008 mm2 500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2241-2248 (2013) - [j40]Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim:
A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3145-3151 (2013) - [j39]Jungmoon Kim, Dong Seok Kim, Chulwoo Kim:
A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3354-3367 (2013) - [j38]Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim:
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 173-177 (2013) - [j37]Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim:
An On-Chip Network Fabric Supporting Coarse-Grained Processor Array. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 178-182 (2013) - [j36]Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim:
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 575-579 (2013) - [j35]Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim:
Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1234-1245 (2013) - [j34]Kisoo Kim, Hokyu Lee, Chulwoo Kim:
366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1950-1954 (2013) - [j33]Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim:
10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2080-2093 (2013) - [c44]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim:
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. ASP-DAC 2013: 89-90 - [c43]Jungmoon Kim, Chulwoo Kim:
A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting. ASP-DAC 2013: 107-108 - [c42]Hyun-Ho Lee, Young-Chai Ko, Jun Heo, Soo-Won Kim, Chulwoo Kim:
Robust transceiver based on worst-case SINR optimization for MIMO interfering broadcast channels with imperfect channel knowledge. ICSPCS 2013: 1-4 - [c41]Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC 2013: 312-313 - 2012
- [j32]Young-Jae Min, Hoon Ki Kim, Chulwoo Kim, Soo-Won Kim, Gil-Su Kim:
A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison. J. Circuits Syst. Comput. 21(8) (2012) - [j31]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. IEEE J. Solid State Circuits 47(1): 131-140 (2012) - [j30]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. IEEE J. Solid State Circuits 47(5): 1199-1208 (2012) - [j29]Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012) - [j28]Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim:
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 270-283 (2012) - [j27]Moo-young Kim, Hokyu Lee, Chulwoo Kim:
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 737-741 (2012) - [j26]Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi, Jong-Pil Son, Chulwoo Kim, Soo-Won Kim:
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1524-1528 (2012) - [c40]Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim:
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS. ISCAS 2012: 1959-1962 - [c39]Debashis Dhar, Inhwa Jung, Chulwoo Kim:
A TDC-based skew compensation technique for high-speed output driver. ISOCC 2012: 61-64 - [c38]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50 - 2011
- [j25]Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(11): 2560-2570 (2011) - [j24]Jungmoon Kim, Jihwan Kim, Chulwoo Kim:
A Regulated Charge Pump With a Low-Power Integrated Optimum Power Point Tracking Algorithm for Indoor Solar Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 802-806 (2011) - [j23]Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim:
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1310-1315 (2011) - [j22]Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim:
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1438-1447 (2011) - [c37]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS. ISSCC 2011: 360-362 - [c36]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. ISSCC 2011: 502-504 - 2010
- [j21]Phi-Hung Pham, Jongsun Park, Chulwoo Kim:
ProMINoC: An efficient Network-on-Chip design for flexible data permutation. IEICE Electron. Express 7(12): 861-866 (2010) - [j20]Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 120-125 (2010) - [j19]Youngsun Han, Peter Harliman, Seon Wook Kim, Jong-Kook Kim, Chulwoo Kim:
A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1020-1024 (2010) - [j18]Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, Chulwoo Kim:
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1130-1134 (2010) - [c35]Dong Seok Kim, Jungmoon Kim, Jihwan Kim, Chulwoo Kim:
An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications. APCCAS 2010: 500-503 - [c34]Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864
2000 – 2009
- 2009
- [j17]Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim:
A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC. IEEE J. Solid State Circuits 44(9): 2437-2451 (2009) - [j16]Jabeom Koo, Sunghwa Ok, Chulwoo Kim:
A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 21-25 (2009) - [j15]Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim:
A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays. IEEE Trans. Circuits Syst. II Express Briefs 56-II(10): 773-777 (2009) - [j14]Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1461-1469 (2009) - [c33]Kisoo Kim, Hokyu Lee, Sangdon Jung, Chulwoo Kim:
A 366kS/s 400uW 0.0013mm2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock. CICC 2009: 203-206 - [c32]Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim:
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. CICC 2009: 243-246 - [c31]Phi-Hung Pham, Phuong Mau, Chulwoo Kim:
A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications. CICC 2009: 645-648 - [c30]Jabeom Koo, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. CICC 2009: 717-720 - [c29]Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim:
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. ISCAS 2009: 1-4 - 2008
- [j13]Dongsuk Shin, Soo-Won Kim, Chulwoo Kim:
Wide frequency range duty cycle correction circuit for DDR interface. IEICE Electron. Express 5(8): 254-259 (2008) - [j12]Hyunho Chu, Jungmoon Kim, Chulwoo Kim:
A monolithic voltage-mode DC-DC converter with a novel oscillator and ramp generator. IEICE Electron. Express 5(17): 683-688 (2008) - [j11]Inhwa Jung, Gunok Jung, Janghoon Song, Moo-young Kim, Junyoung Park, Sung-Bae Park, Chulwoo Kim:
A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 116-120 (2008) - [c28]Inhwa Jung, Moo-young Kim, Chulwoo Kim:
A 1.2GHz delayed clock generator for high-speed microprocessors. ASP-DAC 2008: 95-96 - [c27]Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A slew-rate controlled output driver with one-cycle tuning time. ASP-DAC 2008: 99-100 - [c26]Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim:
A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation. CICC 2008: 455-458 - [c25]Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim:
A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor. CICC 2008: 551-554 - [c24]Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim:
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. ESSCIRC 2008: 82-85 - [c23]Taeyoon Kim, Wonki Park, Heesun Ahn, Kyongwon Min, Sangyong Lee, Jongchan Choi, Chulwoo Kim, Kynnyun Kim, Sungchul Lee:
A 110 dB, 3-mW fourth-order Σ-Δ modulator for atmospheric pressure sensor. SoC 2008: 1-4 - 2007
- [j10]Gil-Su Kim, Chulwoo Kim, Soo-Won Kim:
An automatic threshold-converged CMOS optical receiver for high-definition digital audio interfaces. IEICE Electron. Express 4(22): 690-695 (2007) - [j9]Dongkyu Park, Seoksoo Yoon, Inhwa Jung, Chulwoo Kim:
Noise-Aware Split-Path Domino Logic and its Clock Delaying Scheme. J. Circuits Syst. Comput. 16(1): 139-154 (2007) - [j8]Inhwa Jung, Moo-young Kim, Chulwoo Kim:
Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC). J. Circuits Syst. Comput. 16(2): 169-179 (2007) - [c22]Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. CICC 2007: 369-372 - [c21]Hyunsoo Chae, Sangdon Jung, Chulwoo Kim:
A wide-range duty-independent all-digital multiphase clock generator. ESSCIRC 2007: 186-189 - [c20]Pilsung Choe, Chulwoo Kim, Mark R. Lehto, Jan P. Allebach:
Experimental Comparison of Adaptive vs. Static Thumbnail Displays. HCI (2) 2007: 41-48 - [c19]Chulwoo Kim, Pilsung Choe, Mark R. Lehto, Jan P. Allebach:
Effect of Providing a Web-Based Collaboration Medium for Remote Customer Troubleshooting Tasks. HCI (9) 2007: 47-53 - [c18]Chulwoo Kim, Mark R. Lehto:
Decision Theoretic Perspective on Optimizing Intelligent Help. HCI (3) 2007: 358-365 - [c17]Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. ISSCC 2007: 184-595 - [c16]Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim:
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. ISSCC 2007: 408-611 - 2006
- [j7]Inhwa Jung, Moo-young Kim, Dongsuk Shin, Seon Wook Kim, Chulwoo Kim:
A New Energy x Delay-Aware Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1552-1557 (2006) - [j6]Pilsung Choe, Chulwoo Kim, Mark R. Lehto, Xinran Lehto, Jan P. Allebach:
Evaluating and Improving a Self-Help Technical Support Web Site: Use of Focus Group Interviews. Int. J. Hum. Comput. Interact. 21(3): 333-354 (2006) - [j5]Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim:
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEE J. Solid State Circuits 41(9): 2077-2082 (2006) - [c15]Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim:
High Performance and Area-Efficient Circuit-Switched Network on Chip Design. CIT 2006: 243 - [c14]Janghoon Song, Gilwon Yoon, Chulwoo Kim:
An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling. CICC 2006: 253-256 - [c13]Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim:
A Compact and High Performance Switch for Circuit-Switched Network-On-Chip. SoCC 2006: 53-56 - 2005
- [c12]Youngsun Han, Seon Kim, Chulwoo Kim:
Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing. ICESS 2005: 386-397 - [c11]Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim:
Differential Pass Transistor Pulsed Latch. SoCC 2005: 295-300 - 2004
- [j4]In-Chul Hwang, Chulwoo Kim, Sung-Mo Kang:
A CMOS self-regulating VCO with low supply sensitivity. IEEE J. Solid State Circuits 39(1): 42-48 (2004) - [c10]Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim:
Charge-Sharing-Problem Reduced Split-Path Domino Logic. VLSI Design 2004: 201- - 2003
- [j3]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic with dual Vt: design and synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 64-70 (2003) - [c9]Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Response Time Accelerator with Full Resolution for LCD Panel. PATMOS 2003: 319-327 - [c8]Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim:
Low Power Cache with Successive Tag Comparison Algorithm. PATMOS 2003: 599-606 - [c7]Jaegeun Oh, Seon Wook Kim, Chulwoo Kim:
OpenMP and Compilation Issue in Embedded Applications. WOMPAT 2003: 109-121 - 2002
- [j2]Chulwoo Kim, Sung-Mo Kang:
A low-swing clock double-edge triggered flip-flop. IEEE J. Solid State Circuits 37(5): 648-652 (2002) - [j1]Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang:
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator. IEEE J. Solid State Circuits 37(11): 1414-1420 (2002) - 2001
- [b1]Chulwoo Kim:
Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip. University of Illinois Urbana-Champaign, USA, 2001 - [c6]Chulwoo Kim, Sung-Mo Kang:
A low-power reduced swing single clock flip-flop. ISCAS (4) 2001: 806-809 - [c5]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt. ISCAS (4) 2001: 882-885 - [c4]Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures. ISCAS (4) 2001: 938-941 - 2000
- [c3]Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ICCD 2000: 59-64 - [c2]Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. ISCAS 2000: 756-759
1990 – 1999
- 1999
- [c1]Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang:
NMOS Energy Recovery Logic. Great Lakes Symposium on VLSI 1999: 310-313
Coauthor Index
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