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ORCIDJinuk Luke Shin
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2020 – today
- 2023
[c15]Zhengyu Chen, Dawei Huang, Mingran Wang, Bowen Yang, Jinuk Luke Shin, Changran Hu, Bo Li, Raghu Prabhakar, Gao Deng, Yongning Sheng, Sihua Fu, Lu Yuan, Tian Zhao, Yun Du, Chen Liu, Jun Yang, Viren Shah, Venkat Srinivasan, Sumti Jairath:
AI SoC Design Challenges in the Foundation Model Era. CICC 2023: 1-8- 2022
- [c14]Raghu Prabhakar, Sumti Jairath, Jinuk Luke Shin:
SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0. ISSCC 2022: 350-352
2010 – 2019
- 2016
- [j8]Edith Beigné
, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe:
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51(1): 3-7 (2016) - 2015
- [c13]Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang:
4.3 Fine-grained adaptive power management of the SPARC M7 processor. ISSCC 2015: 1-3 - [c12]Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3 - [c11]Atsuki Inoue, Jinuk Luke Shin:
Session 4 overview: Processors: High-performance digital subcommittee. ISSCC 2015: 68-69 - 2014
- [j7]Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. IEEE J. Solid State Circuits 49(1): 19-31 (2014) - [c10]Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin:
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. A-SSCC 2014: 373-376 - 2013
- [j6]Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister:
The Next Generation 64b SPARC Core in a T4 SoC Processor. IEEE J. Solid State Circuits 48(1): 82-90 (2013) - [c9]Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
3.6GHz 16-core SPARC SoC processor in 28nm. ISSCC 2013: 48-49 - [c8]Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin:
Bandwidth and power management of glueless 8-socket SPARC T5 system. ISSCC 2013: 58-59 - 2012
- [c7]Joshua Friedrich, Jinuk Luke Shin:
Session 3 overview: Processors: High performance digital subcommittee. ISSCC 2012: 54-55 - [c6]Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister:
The next-generation 64b SPARC core in a T4 SoC processor. ISSCC 2012: 60-62 - 2011
- [j5]Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway W. Tam, Alan P. Smith, Ha Pham, Hongping Penny Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong:
A 40 nm 16-Core 128-Thread SPARC SoC Processor. IEEE J. Solid State Circuits 46(1): 131-144 (2011) - 2010
- [c5]Jinuk Luke Shin, Kenway W. Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Penny Li, Alan P. Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong:
A 40nm 16-core 128-thread CMT SPARC SoC processor. ISSCC 2010: 98-99
2000 – 2009
- 2007
- [j4]Ana Sonia Leon, Kenway W. Tam, Jinuk Luke Shin, David Weisner, Francis Schumacher:
A Power-Efficient High-Throughput 32-Thread SPARC Processor. IEEE J. Solid State Circuits 42(1): 7-16 (2007) - 2006
- [c4]Ana Sonia Leon, Brian Langley, Jinuk Luke Shin:
The UltraSPARC T1 Processor: CMT Reliability. CICC 2006: 555-562 - [c3]Ana Sonia Leon, Jinuk Luke Shin, Kenway W. Tam, William Bryg, Francis Schumacher, Poonacha Kongetira, David Weisner, Allan Strong:
A Power-Efficient High-Throughput 32-Thread SPARC Processor. ISSCC 2006: 295-304 - 2005
- [j3]Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon:
A dual-core 64-bit ultraSPARC microprocessor for dense server applications. IEEE J. Solid State Circuits 40(1): 7-18 (2005) - [j2]Jinuk Luke Shin, Bruce Petrick, Mandeep Singh, Ana Sonia Leon:
Design and implementation of an embedded 512-KB level-2 cache subsystem. IEEE J. Solid State Circuits 40(9): 1815-1820 (2005) - 2004
- [c2]Jinuk Luke Shin, Bruce Petrick, Howard Levy, Jinseung Son, Mandeep Singh, Vikas Mathur, Jung-Cheng Yeh, Heesung Choi, Vishal Gupta, Tom Ziaja, Ana Sonia Leon:
Design and implementation of an embedded 512KB level 2 cache subsystem. CICC 2004: 349-352 - [c1]Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon:
A dual-core 64b ultraSPARC microprocessor for dense server applications. DAC 2004: 673-677 - 2001
- [j1]Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi:
Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. IEEE J. Solid State Circuits 36(11): 1738-1744 (2001)
Coauthor Index
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