"Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted ..."

Kenichi Osada et al. (2001)

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DOI: 10.1109/4.962296

access: closed

type: Journal Article

metadata version: 2022-04-06

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Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi:
Universal-V_dd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. IEEE J. Solid State Circuits 36(11): 1738-1744 (2001)

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