"Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a ..."

Yifan YangGong et al. (2014)

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DOI: 10.1109/ASSCC.2014.7008938

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin:
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. A-SSCC 2014: 373-376

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