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2020 – today
- 2024
[c14]Jeesun Oh
, Wooseok Kim, Sungbae Kim, Hyeonjeong Im, Sangsu Lee:
Better to Ask Than Assume: Proactive Voice Assistants' Communication Strategies That Respect User Agency in a Smart Home Environment. CHI 2024: 846:1-846:17- 2023
- [c13]Wooseok Kim, Jian Jun, Minha Lee, Sangsu Lee:
"I Won't Go Speechless": Design Exploration on a Real-Time Text-To-Speech Speaking Tool for Videoconferencing. CHI 2023: 632:1-632:20 - [c12]Jihwan Kim, Hyun Bin Kim, Dengyang Lu, Byeong Woon Lee, Wooseok Kim, Sang Uk Park, Hee Kyu Lee, Jaejun Lim, Yida Wang, Seunghwan Seo, Sang Min Won:
Utilization of Artifact and Noise Affected Electrocardiogram for Simultaneous Heart Rate Computation and Motion Type Inference. SENSORS 2023: 1-4 - [i1]Wooseok Kim, Taiki Fukiage, Takeshi Oishi:
REF2-NeRF: Reflection and Refraction aware Neural Radiance Field. CoRR abs/2311.17116 (2023) - 2022
- [j4]Donggun Yoo, Wooseok Kim, Sangho Park, Bora Oh, Haejoong Kim, Sangmin Lee:
Anticipatory transport system with hybrid linear and nonlinear forecasting using streaming wafer process data. Appl. Soft Comput. 125: 109122 (2022) - [c11]John Joon Young Chung, Wooseok Kim, Kang Min Yoo, Hwaran Lee, Eytan Adar, Minsuk Chang:
TaleBrush: Visual Sketching of Story Generation with Pretrained Language Models. CHI Extended Abstracts 2022: 172:1-172:4 - [c10]John Joon Young Chung, Wooseok Kim, Kang Min Yoo, Hwaran Lee, Eytan Adar, Minsuk Chang:
TaleBrush: Sketching Stories with Generative Pretrained Language Models. CHI 2022: 209:1-209:19 - 2021
- [c9]Wooseok Kim, Sangsu Lee:
"I Can't Talk Now": Speaking with Voice Output Communication Aid Using Text-to-Speech Synthesis During Multiparty Video Conference. CHI Extended Abstracts 2021: 288:1-288:6 - 2020
- [j3]Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1834-1838 (2020)
2010 – 2019
- 2018
- [c8]Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS 2018: 263-266 - [c7]Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko:
A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. ISSCC 2018: 120-122 - 2017
- [j2]Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 655-659 (2017) - 2015
- [c6]Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park:
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. ISSCC 2015: 1-3 - [c5]Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park:
14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. ISSCC 2015: 1-3 - 2014
- [j1]Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits 49(3): 657-672 (2014) - [c4]Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. CICC 2014: 1-4 - 2013
- [c3]Wooseok Kim, Joohan Kim, Minsu Choi, Ik Joon Chang, Jinsang Kim:
Low complexity image correction using color and focus matching for stereo video coding. ISCAS 2013: 2912-2915 - [c2]Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. ISSCC 2013: 250-251
2000 – 2009
- 2009
- [c1]Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim:
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. CICC 2009: 243-246
Coauthor Index
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