"A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth ..."

Junyoung Song et al. (2017)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2016.2580713

access: closed

type: Journal Article

metadata version: 2020-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/SongLHK17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/SongLHK17
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 344-353 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.