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2020 – today
- 2024
[j18]Jongchan An
, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song:
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1169-1172 (2024)- 2021
- [j17]Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim:
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9: 118907-118918 (2021) - [j16]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1567-1574 (2021) - [c8]Nevada Sanchez, Kailiang Chen, Chao Chen, Dan McMahill, Sewook Hwang, Joseph Lutsky, Jungwook Yang, Liewei Bao, Leung Kin Chiu, Graham Peyton, Hamid Soleimani, Bob Ryan, J. R. Petrus, Youn-Jae Kook, Tyler S. Ralston, Keith Fife, Jonathan Rothberg:
34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound. ISSCC 2021: 480-482
2010 – 2019
- 2019
- [j15]Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54(2): 463-475 (2019) - [j14]Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 192-196 (2019) - 2018
- [j13]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 331-342 (2018) - 2017
- [j12]Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim:
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 650-654 (2017) - [j11]Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2691-2702 (2017) - [j10]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 344-353 (2017) - [c7]Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim:
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC 2017: 490-491 - 2016
- [j9]Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1092-1103 (2016) - [j8]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2768-2777 (2016) - [c6]Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim:
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits 2016: 1-2 - 2015
- [c5]Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim:
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC 2015: 1-3 - 2014
- [j7]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 865-869 (2014) - [j6]Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim:
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2156-2163 (2014) - 2013
- [j5]Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim:
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 268-278 (2013) - [j4]Young-Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim:
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 303-313 (2013) - [j3]Sewook Hwang, Jabeom Koo, Kisoo Kim, Hokyu Lee, Chulwoo Kim:
A 0.008 mm2 500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2241-2248 (2013) - [j2]Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim:
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 575-579 (2013) - [c4]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim:
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. ASP-DAC 2013: 89-90 - [c3]Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC 2013: 312-313 - 2012
- [j1]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. IEEE J. Solid State Circuits 47(5): 1199-1208 (2012) - [c2]Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim:
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS. ISCAS 2012: 1959-1962 - 2011
- [c1]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS. ISSCC 2011: 360-362
Coauthor Index
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