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2020 – today
- 2020
[j5]Jaehun Jun, Sangsu Lee, Chulwoo Kim:
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system. IET Circuits Devices Syst. 14(2): 155-158 (2020)- [j4]Jaegeun Song, Jaehun Jun, Chulwoo Kim
:
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1184-1188 (2020)
2010 – 2019
- 2019
- [j3]Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54(2): 463-475 (2019) - [c3]Malik Summair Asghar, Saad Arslan, HyungWon Kim, Jaehun Jun, Hyunkyu Park:
Hybrid Concurrent Driving Technique for Large Touch Screen Panels. ISOCC 2019: 79-80 - 2018
- [j2]Jaehun Jun, Jaegeun Song, Chulwoo Kim:
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1567-1580 (2018) - [j1]Jaehun Jun, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1509-1513 (2018) - 2017
- [c2]Sangsu Lee, Jaehun Jun, Chulwoo Kim:
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. ISOCC 2017: 180-181 - [c1]Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim:
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC 2017: 490-491
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