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ORCIDJong-Ho Kang
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2010 – 2019
- 2015
[j1]Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, Gunwoo Park, Yunsaing Kim:
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel. IEEE J. Solid State Circuits 50(11): 2613-2624 (2015)- [c6]Junho Cheon, Insoo Lee, Changyong Ahn, Milos Stanisavljevic, Aravinthan Athmanathan, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong-Ho Kang, Jun Hyun Chun:
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology. CICC 2015: 1-4 - [c5]Dong-Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung Whan Kim, Jong-Ho Kang, Jaejin Lee, Jun Hyun Chun:
Design considerations of HBM stacked DRAM and the memory architecture extension. CICC 2015: 1-8 - 2014
- [c4]Hyunbae Lee, Taeksang Song, Sangyeon Byeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, Koeun Cheon, Donghwan Seol, Jong-Ho Kang, Gunwoo Park, Yunsaing Kim:
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel. A-SSCC 2014: 125-128 - [c3]Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC 2014: 1-4 - 2012
- [c2]Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong:
A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44 - [c1]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50
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