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Kyu-Nam Lim

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2010 – 2019

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2012
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  - conf/isscc/LimJWLKKCKKPJ12
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Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong:
A 1.2V 23nm 6F² 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44

1990 – 1999

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1999
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Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho:
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE J. Solid State Circuits 34(11): 1589-1599 (1999)

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