"A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM."

Hongil Yoon et al. (1999)

> Home

Details and statistics

DOI: 10.1109/4.799867

access: closed

type: Journal Article

metadata version: 2022-07-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/YoonCYKKLLLJJJC99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/YoonCYKKLLLJJJC99
Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho:
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE J. Solid State Circuits 34(11): 1589-1599 (1999)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.