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ORCIDIEEE Journal of Solid-State Circuits, Volume 44
Volume 44, Number 1, January 2009
- Donhee Ham
, Hideto Hidaka, Ron Ho, Ram K. Krishnamurthy:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. 3-6 - Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar:
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. 7-17 - Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer:
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. 18-31 - Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw:
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. 32-48 - Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. 49-63 - Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. 64-72 - Gianfranco Gerosa, Steve Curtis, Michael D'Addeo, Bo Jiang, Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed H. Taufique, Haytham Samarchi:
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS. 73-82 - Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama:
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. 83-89 - Anders Nilsson, Eric Tell, Dake Liu:
An 11 mm2, 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS. 90-97 - Christian Benkeser, Andreas Burg, Teo Cupaiuolo, Qiuting Huang:
Design and Optimization of an HSDPA Turbo Decoder ASIC. 98-106 - Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar:
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. 107-114 - Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan:
A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter. 115-126 - Chih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Liang-Gee Chen:
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor. 127-135 - Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Hoi-Jun Yoo:
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine. 136-147 - Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr:
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. 148-154 - Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John A. Gabric, Daniel Geise, Steve Lamphier, Yue Tan:
An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. 155-162 - Naveen Verma, Anantha P. Chandrakasan:
A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing. 163-173 - Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. 174-185 - Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jonghak Yuh, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffrey Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader:
A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. 186-194 - Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader:
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. 195-207 - Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim:
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. 208-216 - Ferdinando Bedeschi, Rich Fackenthal, Claudio Resta, Enzo Michele Donzè, Meenatchi Jagasivamani, Egidio Cassiodoro Buda, Fabio Pellizzer, David W. Chow, Alessandro Cabrini, Giacomo Matteo Angelo Calvi, Roberto Faravelli, Andrea Fantini, Guido Torelli, Duane Mills, Roberto Gastaldi, Giulio Casagrande:
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage. 217-227 - David Ruffieux, Jérémie Chabloz, Matteo Contaldo, Claude Müller, Franz-Xaver Pengg, Paola Tortori, Alexandre Vouilloz, Patrick Volet, Christian C. Enz:
A Narrowband Multi-Channel 2.4 GHz MEMS-Based Transceiver. 228-239 - Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst:
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters. 240-246 - Éric Colinet, Cedric Durand, Laurent Duraffourg, Patrick Audebert, Guillaume Dumas, Fabrice Casset, Eric Ollier, Pascal Ancey, Jean-François Carpentier, Lionel Buchaillot, Adrian M. Ionescu:
Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process. 247-257 - Jongmin Park, Taejoong Song, Joonhoi Hur, Sang Min Lee, Jungki Choi, Kihong Kim, Kyutae Lim, Chang-Ho Lee, Haksun Kim, Joy Laskar:
A Fully Integrated UHF-Band CMOS Receiver With Multi-Resolution Spectrum Sensing (MRSS) Functionality for IEEE 802.22 Cognitive Radio Applications. 258-268 - Nathan Pletcher, Simone Gambini, Jan M. Rabaey:
A 52 µW Wake-Up Receiver With -72 dBm Sensitivity Using an Uncertain-IF Architecture. 269-280 - Heinz-Gerd Graf, Christine Harendt, Thorsten Engelhardt, Cor Scherjon, Karsten Warkentin, Harald Richter, Joachim N. Burghartz:
High Dynamic Range CMOS Imager Technologies for Biomedical Applications. 281-289 - Albrecht Rothermel, Liu Liu, Naser Pour Aryan, Michael Fischer, Juergen Wuenschmann, Steffen Kibbel, Alex Harscher:
A CMOS Chip With Active Pixel Array and Specific Test Features for Subretinal Implantation. 290-300 - Clint L. Schow, Fuad E. Doany, Chen Chen, Alexander V. Rylyakov, Christian W. Baks, Daniel M. Kuchta, Richard A. John, Jeffrey A. Kash:
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link. 301-313
Volume 44, Number 2, February 2009
- Bram Nauta:
New Associate Editor. 319 - Heng Zhang, Xiaohua Fan, Edgar Sánchez-Sinencio:
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique. 320-330 - Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. 331-343 - Jonathan Borremans, Steven Thijs, Piet Wambacq, Yves Rolain, Dimitri Linten, Maarten Kuijk:
A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA. 344-353 - Raymond E. Barnett, Jin Liu, Steve Lazar:
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders. 354-370 - Kenneth A. Townsend, James W. Haslett:
A Wideband Power Detection System Optimized for the UWB Spectrum. 371-381 - Nobuo Sasaki, Kentaro Kimoto, Wataru Moriyama, Takamaro Kikkawa:
A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection. 382-393 - Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda:
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. 394-403 - Jennifer N. Kitchen, Connie Chu, Sayfe Kiaei, Bertan Bakkaloglu:
Combined Linear and Δ-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters. 404-413 - Hui Zheng, Shuzuo Lou, Dongtian Lu, Cheng Shen, Tatfu Chan, Howard C. Luong:
A 3.1 GHz-8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-µm CMOS Process. 414-426 - Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. 427-435 - Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz:
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. 436-449 - ChuanKang Liang, Behzad Razavi:
Systematic Transistor and Inductor Modeling for Millimeter-Wave Design. 450-457 - Youngcheol Chae, Gunhee Han:
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator. 458-472 - Martin Anderson, Lars Sundström:
Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback. 473-483 - Josep Rius, Maurice Meijer:
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors. 484-494 - Hesam Amir Aslanzadeh, Erik John Pankratz, Edgar Sánchez-Sinencio:
A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF. 495-508 - Chang-Seok Chae, Hanh-Phuc Le, Kwang-Chan Lee, Gyu-Ha Cho, Gyu-Hyeong Cho:
A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels. 509-524 - Chih-Wen Lu:
A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers. 525-537 - Armin Tajalli, Yusuf Leblebici:
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. 538-548 - Sotirios Zogopoulos, Won Namgoong:
High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding. 549-557 - Zheng Xu, Kenneth L. Shepard:
Design and Analysis of Actively-Deskewed Resonant Clock Networks. 558-568 - Radu Zlatanovici, Sean Kao, Borivoje Nikolic:
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example. 569-583 - Xiongfei Meng, Resve A. Saleh:
An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. 584-593 - Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga:
HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis. 594-608 - Mohammad Sharifkhani, Manoj Sachdev:
SRAM Cell Stability: A Dynamic Perspective. 609-619 - Mohammad Sharifkhani, Manoj Sachdev:
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. 620-630 - Stanley Schuster, Richard E. Matick:
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier. 631-641 - Ya-Chun Lai, Shi-Yu Huang:
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT). 642-649 - Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. 650-658 - Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan:
A 32-µW 1.83-kS/s Carbon Nanotube Chemical Sensor System. 659-669
Volume 44, Number 3, March 2009
- Tae Wook Kim, Harish Muthali, Susanta Sengupta, Kenneth Barnett, James Jaffee:
Multi-Standard Mobile Broadcast Receiver LNA With Integrated Selectivity and Novel Wideband Impedance Matching Technique. 675-685 - Donggu Im, Ilku Nam, Hong-Teuk Kim, Kwyro Lee:
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner. 686-698 - Osama Shana'a:
A 2.4-2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters. 699-707 - Namjun Cho, Long Yan, Joonsung Bae, Hoi-Jun Yoo:
A 60 kb/s-10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication. 708-717 - Daniel L. Kaczman, Manish Shah, Mohammed Alam, Mohammed Rachedine, David L. Cashen, Lu M. Han, Anand Raghavan:
A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and +90 dBm IIP2. 718-739 - Ming-Ching Kuo, Shiau-Wen Kao, Chih-Hung Chen, Tsung-Shuen Hung, Yi-Shing Shih, Tzu-Yi Yang, Chien-Nan Kuo:
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µm CMOS. 740-750 - Ali Parsa, Behzad Razavi:
A New Transceiver Architecture for the 60-GHz Band. 751-762 - Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. 763-774 - Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu:
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. 775-783 - Ibrahim R. Chamas, Sanjay Raman:
Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO). 784-796 - Li-min Lee, Chih-Kong Ken Yang:
An LC-Based Clock Buffer With Tunable Injection Locking. 797-807 - Yunliang Zhu, Jonathan D. Zuegel, John R. Marciante, Hui Wu:
Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation. 808-823 - Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto:
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. 824-834 - Sami Kurtti, Juha Kostamovaara:
Laser Radar Receiver Channel With Timing Detector Based on Front End Unipolar-to-Bipolar Pulse Shaping. 835-847 - Hüseyin Dinc, Phillip E. Allen:
A 1.2 GSample/s Double-Switching CMOS THA With -62 dB THD. 848-861 - Zhiheng Cao, Shouli Yan, Yunchu Li:
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS. 862-873 - Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. 874-882 - Byung-Geun Lee, Robin M. Tsang:
A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-gm Opamp. 883-890 - Song-Bok Kim, Stefan Joeres, Ralf Wunderlich, Stefan Heinen:
A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 µm CMOS. 891-900 - Aida Varzaghani, Chih-Kong Ken Yang:
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. 901-915 - Kyehyung Lee, Qingdong Meng, Tetsuro Sugimoto, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Un-Ku Moon, Gabor C. Temes:
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. 916-927 - Ronan A. R. van der Zee, Fred Mostert:
Output Impedance Shaping for Frequency Compensation of MOS Audio Power Amplifiers. 928-934 - Giby Samson, Lawrence T. Clark:
Low-Power Race-Free Programmable Logic Arrays. 935-946 - Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. 947-955 - Chang-Tzu Wang, Ming-Dou Ker:
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. 956-964 - Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan:
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. 965-976 - Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara:
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. 977-986 - Meng-Fan Chang, Shin-Jang Shen:
A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme. 987-994 - Joseph N. Y. Aziz, Karim Abdelhalim, Ruslana Shulyzki, Roman Genov, Berj L. Bardakjian, Miron Derchansky, Demitre Serletis, Peter L. Carlen:
256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes. 995-1005 - Andreas G. Katsiamis, Emmanuel M. Drakakis, Richard F. Lyon:
A Biomimetic, 4.5µW, 120+ dB, Log-Domain Cochlea Channel With AGC. 1006-1022
Volume 44, Number 4, April 2009
- Katsu Nakamura, Masayuki Mizuno:
Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits. 1039-1040 - Chun-Ying Chen, Michael Q. Le, Kwang Young Kim:
A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration. 1041-1046 - Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen, Edward J. F. Paulus:
A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS. 1047-1056 - Jason Hu, Noam Dolev, Boris Murmann:
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification. 1057-1066 - Xiaodan Zou, Xiaoyuan Xu, Libin Yao, Yong Lian:
A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip. 1067-1077 - Hyunsik Park, Ki Young Nam, David K. Su, Katelijn Vleugels, Bruce A. Wooley:
A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator. 1078-1088 - Matthew Z. Straayer, Michael H. Perrott:
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. 1089-1098 - Ming-Hsin Huang, Ke-Horng Chen:
Single-Inductor Multi-Output (SIMO) DC-DC Converters With High Light-Load Efficiency and Minimized Cross-Regulation for Portable Devices. 1099-1111 - Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation. 1112-1120 - Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar:
Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking. 1121-1129 - Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas:
A 167-Processor Computational Platform in 65 nm CMOS. 1130-1144 - Scott Hanson, Mingoo Seok, Yu-Shiang Lin, Zhiyoong Foo, Daeyeon Kim, Yoonmyung Lee, Nurrachman Liu, Dennis Sylvester, David T. Blaauw:
A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode. 1145-1155 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling. 1156-1166 - Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton:
An Asynchronous Power Aware and Adaptive NoC Based Circuit. 1167-1177 - Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue:
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support. 1178-1183 - Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe:
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. 1184-1191 - Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe:
A 0.7 V Single-Supply SRAM With 0.495 µm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme. 1192-1198 - Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De:
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. 1199-1208 - Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi:
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. 1209-1215 - Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. 1216-1226 - Ken Takeuchi:
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD). 1227-1234 - Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. 1235-1247 - Jose L. Bohorquez, Anantha P. Chandrakasan, Joel L. Dawson:
A 350 µW CMOS MSK Transmitter and 400 µW OOK Super-Regenerative Receiver for Medical Implant Communications. 1248-1259 - Mohammad E. Heidari, Minjae Lee, Asad A. Abidi:
All-Digital Outphasing Modulator for a Software-Defined Transmitter. 1260-1271 - Rameswor Shrestha, Ronan A. R. van der Zee, Anton de Graauw, Bram Nauta:
A Wideband Supply Modulator for 20 MHz RF Bandwidth Polar PAs in 65 nm CMOS. 1272-1280 - David A. Sobel, Robert W. Brodersen:
A 1 Gb/s Mixed-Signal Baseband Analog Front-End for a 60 GHz Wireless Receiver. 1281-1289 - Fang Lin, Xinyu Yu, Sumant Ranganathan, Tom Kwan:
A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS. 1290-1297 - Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. 1298-1305 - Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi, Francesco Svelto:
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. 1306-1315
Volume 44, Number 5, May 2009
- Albert C. Jerng:
Overview for the Special Section on the 2008 Radio Frequency Integrated Circuits Symposium. 1319-1320 - Fred Tzeng, Amin Jahanian, Deyi Pi, Payam Heydari:
A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End. 1321-1335 - Frank Zhang, Anuranjan Jha, Ranjit Gharpurey, Peter R. Kinget:
An Agile, Ultra-Wideband Pulse Radio Transceiver With Discrete-Time Wideband-IF. 1336-1351 - Adil A. Kidwai, Chang-Tsung Fu, Jonathan C. Jensen, Stewart S. Taylor:
A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process. 1352-1360 - Hsin-Hsing Liao, Hao Jiang, Payman Shanjani, Joseph King, Arya Behzad:
A Fully Integrated 2×2 Power Amplifier for Dual Band MIMO 802.11n WLAN Application Using SiGe HBT Technology. 1361-1371 - Melina Apostolidou, Mark P. van der Heijden, Domine M. W. Leenaerts, Jan Sonsky, Anco Heringa, Iouri Volokhine:
A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off. 1372-1379 - Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Peter R. Kinget:
Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 µm CMOS. 1380-1390 - Belal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott:
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop. 1391-1400 - Adam Hart, Sorin P. Voinigescu:
A 1 GHz Bandwidth Low-Pass ΔΣADC With 20-50 GHz Adjustable Sampling Rate. 1401-1414 - Andries J. Scholten, Geert D. J. Smit, Bart A. De Vries, Luuk F. Tiemeijer, Jeroen A. Croon, Dirk B. M. Klaassen, Ronald van Langevelde, Xin Li, Weimin Wu, Gennady Gildenblat:
The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications. 1415-1424 - Tim R. LaRocca, Jenny Yi-Chun Liu, Mau-Chung Frank Chang:
60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design. 1425-1435 - Oren Eytan Eliezer, Robert Bogdan Staszewski, Imran Bashir, Sumeer Bhatara, Poras T. Balsara:
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers. 1436-1453 - Pei-Wei Chen, Tser-Yu Lin, Ling-Wei Ke, Rickey Yu, Ming-Da Tsai, Stanley Yeh, Yi-Bin Lee, Bosen Tzeng, Yen-Horng Chen, Sheng-Jui Huang, Yu-Hsin Lin, Guang-Kaai Dehng:
A 0.13 µm CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture. 1454-1463 - Dicle Ozis, Jeyanandh Paramesh, David J. Allstot:
Integrated Quadrature Couplers and Their Application in Image-Reject Receivers. 1464-1476 - Johan Bauwelinck, Els De Backer, Cedric Mélange, Guy Torfs, Peter Ossieur, Xing-Zhi Qiu, Jan Vandewege, Stephan Horvath:
A 1024-QAM Analog Front-End for Broadband Powerline Communication Up to 60 MHz. 1477-1485 - Jan Nissinen, Ilkka Nissinen, Juha Kostamovaara:
Integrated Receiver Including Both Receiver Channel and TDC for a Pulsed Time-of-Flight Laser Rangefinder With cm-Level Accuracy. 1486-1497 - Kwang-Jin Koh, Jason W. May, Gabriel M. Rebeiz:
A Millimeter-Wave (40-45 GHz) 16-Element Phased-Array Transmitter in 0.18-µm SiGe BiCMOS Technology. 1498-1509 - Jeong-Kyoum Kim, Jaeha Kim, Gyudong Kim, Deog-Kyoon Jeong:
A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver. 1510-1521 - Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. 1522-1530 - Chuying Mao, Chakravartula Shashank Nallani, Swaminathan Sankaran, Eunyoung Seok, Kenneth K. O:
125-GHz Diode Frequency Doubler in 0.13-µm CMOS. 1531-1538 - Jri Lee, Huaide Wang:
Study of Subharmonically Injection-Locked PLLs. 1539-1553 - Byeong-Gyu Nam, Hoi-Jun Yoo:
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC. 1554-1570 - Chao-Ching Wang, Chieh-Jen Cheng, Tien-Fu Chen, Jinn-Shyan Wang:
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. 1571-1581 - Massimo Gottardi, Nicola Massari, Syed Arsalan Jawed:
A 100 µW 128 × 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications. 1582-1592 - Ajit Sharma, Faisal Zaman, Farrokh Ayazi:
A Sub-0.2°hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching. 1593-1608 - Giorgio Ferrari, Fabio Gozzini, Alessandro Molari, Marco Sampietro:
Transimpedance Amplifier for High Sensitivity Current Measurements on Nanodevices. 1609-1616 - David Barnhart, Tanya Vladimirova, Martin N. Sweeting, Kenneth S. Stevens:
Radiation Hardening by Design of Asynchronous Logic for Hostile Environments. 1617-1628 - Nan Sun, Yong Liu, Hakho Lee, Ralph Weissleder, Donhee Ham:
CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance. 1629-1643 - Ta-chien Huang, Sebastian Sorgenfrei, Ping Gong, Rastislav Levicky, Kenneth L. Shepard:
A 0.18-µm CMOS Array Sensor for Integrated Time-Resolved Fluorescence Detection. 1644-1654 - Liang-Teck Pang, Borivoje Nikolic:
Measurements and Analysis of Process Variability in 90nmCMOS. 1655-1663
Volume 44, Number 6, June 2009
- Bram Nauta:
New Associate Editor. 1667 - Jeffrey S. Walling, Hasnain Lakdawala, Yorgos Palaskas, Ashoke Ravi, Ofir Degani, Krishnamurthy Soumyanath, David J. Allstot:
A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS. 1668-1678 - Patrick P. Mercier, Denis C. Daly, Anantha P. Chandrakasan:
An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers. 1679-1688 - Hsieh-Hung Hsieh, Liang-Hung Lu:
A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair. 1689-1696 - Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka:
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. 1697-1708 - Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone:
A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. 1709-1720 - David Barras, Robert Meyer-Piening, George von Büren, Walter Hirt, Heinz Jäckel:
A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver. 1721-1733 - Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance. 1734-1744 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform. 1745-1755 - Andrew Poon, Andrew Chang, Hirad Samavati, S. Simon Wong:
Reduction of Inductive Crosstalk Using Quadrupole Inductors. 1756-1764 - Jie Gu, Hanyong Eom, Chris H. Kim:
On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit. 1765-1775 - Sterling R. Whitaker, Lowell H. Miles, Jody W. Gambles, Paul Winterrowd, Ron Nelson, Chad Orbe, Gary K. Maki:
Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder. 1776-1784 - Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode. 1785-1795 - Song Guo, Hoi Lee:
An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants. 1796-1804 - Arjang Hassibi, Aydin Babakhani, Ali Hajimiri:
A Spectral-Scanning Nuclear Magnetic Resonance Imaging (MRI) Transceiver. 1805-1813 - Soumyajit Mandal, Serhii M. Zhak, Rahul Sarpeshkar:
A Bio-Inspired Active Radio-Frequency Silicon Cochlea. 1814-1828 - Alireza Nilchi, Joseph N. Y. Aziz, Roman Genov:
Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. 1829-1839 - Song-Bok Kim:
Correction to "A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 µm CMOS" [Mar 09 891-900]. 1853 - Paul T. M. van Zeijl, Manel Collados:
Comments on "A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth". 1854 - Amirpouya Kavousian:
Reply to Comments on "A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth". 1855
Volume 44, Number 7, July 2009
- Kari A. I. Halonen, Kofi A. A. Makinwa, Stefan Rusu:
Introduction to the Special Issue on the 34th ESSCIRC. 1859-1861 - Nick Van Helleputte, Georges G. E. Gielen:
A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers. 1862-1871 - Yi Zhao, Yunzhi Dong, John F. M. Gerrits, Gerrit van Veenendaal, John R. Long, John R. Farserotu:
A Short Range, Low Data Rate, 7.2 GHz-7.7 GHz FM-UWB Receiver Front-End. 1872-1882 - Calogero D. Presti, Francesco Carrara, Antonino Scuderi, Peter M. Asbeck, Giuseppe Palmisano:
A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control. 1883-1896 - Marco Cassia, Aristotele Hadjichristos, Hong Sun Kim, Jin-Su Ko, Jeongsik Yang, Sang-Oh Lee, Gurkanwal Sahota:
A Low-Power CMOS SAW-Less Quad Band WCDMA/HSPA/HSPA+/1X/EGPRS Transmitter. 1897-1906 - Behzad Mesgarzadeh, Atila Alvandpour:
A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode. 1907-1913 - William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten:
A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery. 1914-1926 - Lucio Rodoni, George von Büren, Alex Huber, Martin L. Schmatz, Heinz Jäckel:
A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS. 1927-1941 - Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. 1942-1949 - Lianming Li, Patrick Reynaert, Michiel S. J. Steyaert:
Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank. 1950-1958 - Domagoj Siprak, Marc Tiebout, Nicola Zanolla, Peter Baumgartner, Claudio Fiegna:
Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias. 1959-1967 - Erik Öjefors, Ullrich R. Pfeiffer, Alvydas Lisauskas, Hartmut G. Roskos:
A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology. 1968-1976 - Cristiano Niclass, Claudio Favi, Theo Kluter, Frédéric Monnier, Edoardo Charbon:
Single-Photon Synchronous Detection. 1977-1989 - Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel S. J. Steyaert:
A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM. 1990-2001 - Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine M. W. Leenaerts, Bram Nauta:
A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios. 2002-2009 - Ahmed Gharbiya, David A. Johns:
A 12-bit 3.125 MHz Bandwidth 0-3 MASH Delta-Sigma Modulator. 2010-2018 - Ybe Creten, Patrick Merken, Willy Sansen, Robert P. Mertens, Chris Van Hoof:
An 8-Bit Flash Analog-to-Digital Converter in Standard CMOS Technology Functional From 4.2 K to 300 K. 2019-2025 - Mahdi Kashmiri, Sha Xia, Kofi A. A. Makinwa:
A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter. 2026-2035 - Viola Schaffer, Martijn F. Snoeij, Mikhail V. Ivanov, Dimitar Trifonov:
A 36 V Programmable Instrumentation Amplifier With Sub-20µV Offset and a CMRR in Excess of 120 dB at All Gain Settings. 2036-2046 - Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. 2047-2054 - Claude Arm, Steve Gyger, Jean-Marc Masgonty, Marc-Nicolas Morgan, Jean-Luc Nagel, Christian Piguet, Flavio Rampogna, Patrick Volet:
Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core. 2055-2064 - Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers. 2065-2077
Volume 44, Number 8, August 2009
- Lawrence T. Clark, Anthony Chan Carusone, Payam Heydari:
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference. 2083-2084 - Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu:
A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link. 2085-2099 - Vipul Jain, Babak Javid, Payam Heydari:
A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars. 2100-2113 - Robert F. Wiser, Masoud Zargari, David K. Su, Bruce A. Wooley:
A 5-GHz Wireless LAN Transmitter with Integrated Tunable High-Q RF Filter. 2114-2125 - Namsoo Kim, Lawrence E. Larson, Vladimir Aparin:
A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA. 2126-2137 - Masum Hossain, Anthony Chan Carusone:
CMOS Oscillators for Clock Distribution and Injection-Locked Deskew. 2138-2153 - Frederic Nabki, Karim Allidina, Faisal Ahmad, Paul-Vahe Cicek, Mourad N. El-Gamal:
A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator. 2154-2168 - Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture. 2169-2181 - Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang:
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. 2182-2192 - Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Hyung Ki Ahn, Byeong-Ha Park, Zhihua Wang:
A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. 2193-2201 - Kyehyung Lee, Matthew R. Miller, Gabor C. Temes:
An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD. 2202-2211 - Nima Maghari, Sunwoo Kwon, Un-Ku Moon:
74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain. 2212-2221 - Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim:
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme. 2222-2232 - Liang-Teck Pang, Kun Qian, Costas J. Spanos, Borivoje Nikolic:
Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology. 2233-2243 - Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. 2244-2250 - Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu:
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. 2251-2259
Volume 44, Number 9, September 2009
- Bram Nauta:
New Associate Editors. 2263-2264 - Donald Y. C. Lie:
Introduction to the Special Section on the 2008 Bipolar/BiCMOS Circuits and Technology Meeting. 2265-2266 - Colin C. McAndrew, Zoltan Huszka, Geoffrey J. Coram:
Bipolar Transistor Excess Phase Modeling in Verilog-A. 2267-2275 - Jerry Lopez, Yan Li, Jeremy D. Popp, Donald Y. C. Lie, Chia-Chang Chuang, Kevin Chen, Stanley Wu, Tzu-Yin Yang, Gin-Kou Ma:
Design of Highly Efficient Wideband RF Polar Transmitters Using the Envelope-Tracking Technique. 2276-2294 - Robert A. Kertis, James S. Humble, Mary A. Daun-Lindberg, Rick A. Philpott, Karl E. Fritz, Daniel J. Schwab, Jason F. Prairie, Barry K. Gilbert, Erik S. Daniel:
A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators. 2295-2311 - Grégory Avenier, Malick Diop, Pascal Chevalier, Germaine Troillard, Nicolas Loubet, Julien Bouvier, Linda Depoyan, Nicolas Derrier, Michel Buczko, Cédric Leyris, Samuel Boret, Sébastien Montusclat, Alain Margain, Sébastien Pruvost, Sean T. Nicolson, Kenneth H. K. Yau, Nathalie Revil, Daniel Gloria, Didier Dutartre, Sorin P. Voinigescu, Alain Chantre:
0.13µm SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications. 2312-2321 - Lis K. Nanver, Hugo Schellevis, Tom L. M. Scholtes, Luigi La Spina, Gianpaolo Lorito, Francesco Sarubbi, Viktor Gonda, Milos Popadic, Koen Buisman, Leo C. N. de Vreede, Cong Huang, Silvana Milosavljevic, Egbert J. G. Goudena:
Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling. 2322-2338 - Jeffrey S. Walling, Stewart S. Taylor, David J. Allstot:
A Class-G Supply Modulator and Class-E PA in 130 nm CMOS. 2339-2347 - Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme. 2348-2355 - Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain:
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration. 2356-2365 - Bibhudatta Sahoo, Behzad Razavi:
A 12-Bit 200-MHz CMOS ADC. 2366-2380 - Yusuke Aiba, Koji Tomioka, Yuta Nakashima, Koichi Hamashita, Bang-Sup Song:
A Fifth-Order Gm-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range. 2381-2391 - Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon:
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. 2392-2401 - Imre Knausz, Robert J. Bowman:
A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers. 2402-2410 - Shih-An Yu, Peter R. Kinget:
A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation. 2411-2425 - Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang:
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators. 2426-2436 - Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim:
A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC. 2437-2451 - Yao-Hong Liu, Tsung-Hsien Lin:
A Wideband PLL-Based G/FSK Transmitter in 0.18 µm CMOS. 2452-2462 - Burak Çatli, Mona Mostafa Hella:
A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators. 2463-2477 - Keng-Jan Hsiao, Tai-Cheng Lee:
An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation. 2478-2487 - Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. 2488-2495 - Masaki Kitsunezuka, Shinichi Hori, Tadashi Maeda:
A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio. 2496-2502 - Hassan O. Elwan, Ahmet Tekin, Kenneth Pedrotti:
A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS. 2503-2514 - Tien-Yu Lo, Chung-Chih Hung, Mohammed Ismail:
A Wide Tuning Range Gm-C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers. 2515-2524 - Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto:
A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter. 2525-2534 - Rida S. Assaad, José Silva-Martínez:
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier. 2535-2542 - Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev:
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. 2543-2553 - Bita Nezamfar, Elad Alon, Mark Horowitz:
Energy-Performance Tunable Logic. 2554-2567 - Chun-Yu Hsieh, Ke-Horng Chen:
Boost DC-DC Converter With Fast Reference Tracking (FRT) and Charge-Recycling (CR) Techniques for High-Efficiency and Low-Cost LED Driver. 2568-2580 - Dongsoo Kim, Gunhee Han:
A 200µs Processing Time Smart Image Sensor for an Eye Tracker Using Pixel-Level Analog Image Processing. 2581-2590 - Amir M. Sodagar, Gayatri E. Perlin, Ying Yao, Khalil Najafi, Kensall D. Wise:
An Implantable 64-Channel Wireless Microsystem for Single-Unit Neural Recording. 2591-2604 - Federico Vecchi, Matteo Repossi, Wissam Eyssa, Paolo Arcioni, Francesco Svelto:
Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations. 2605-2615 - Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. 2616-2623
Volume 44, Number 10, October 2009
- William C. B. Peatman, Erik S. Daniel:
Introduction to the Special Section on the IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2008). 2627-2628 - Jinseong Jeong, Donald F. Kimball, Myoungbo Kwak, Paul Draxler, Chin Hsia, Craig Steinbeiser, Thomas Landon, Oleh Krutko, Lawrence E. Larson, Peter M. Asbeck:
High-Efficiency WCDMA Envelope Tracking Base-Station Amplifier Implemented With GaAs HVHBTs. 2629-2639 - Charles Campbell, Cathy Lee, Victoria Williams, Ming-Yih Kao, Hua-Quen Tserng, Paul Saunier, Tony Balistreri:
A Wideband Power Amplifier MMIC Utilizing GaN on SiC HEMT Technology. 2640-2647 - Kevin W. Kobayashi, YaoChung Chen, Ioulia Smorchkova, Benjamin Heying, Wen-Ben Luo, William Sutton, Mike Wojtowicz, Aaron K. Oki:
A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power. 2648-2654 - Nils Pohl, Hans-Martin Rein, Thomas Musch, Klaus Aufinger, Josef Hausner:
SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency. 2655-2662 - James Chingwei Li, Kenneth R. Elliott, David S. Matthews, Donald A. Hitko, Daniel Zehnder, Yakov Royter, Pamela R. Patterson, Tahir Hussain, Joseph F. Jensen:
100 GHz+ Gain-Bandwidth Differential Amplifiers in a Wafer Scale Heterogeneously Integrated Technology Using 250 nm InP DHBTs and 130 nm CMOS. 2663-2670 - Chia-Ming Tsai:
A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 µm CMOS Technology. 2671-2677 - Ahmad Mirzaei, Hooman Darabi, John C. Leete, Xinyu Chen, Kevin Juan, Ahmad Yazdi:
Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers. 2678-2688 - Ahmet Tekin, Hassan O. Elwan, Aly Ismail, Kenneth Pedrotti:
Noise-Shaping Gain-Filtering Techniques for Integrated Receivers. 2689-2701 - Takahide Terada, Ryosuke Fujiwara, Goichi Ono, Takayasu Norimatsu, Tatsuo Nakagawa, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver. 2702-2710 - Wu-Hsin Chen, Sanghoon Joo, Serkan Sayilir, Russell Willmot, Tae-Young Choi, Dowon Kim, Julia Hsin-Lin Lu, Dimitrios Peroulis, Byunghoo Jung:
A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas. 2711-2721 - Antoine Frappé, Axel Flament, Bruno Stefanelli, Andreas Kaiser, Andreia Cathelin:
An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators. 2722-2732 - Debopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad:
Design Considerations for 60 GHz Transformer-Coupled CMOS Power Amplifiers. 2733-2744 - Enrique Prefasi, Luis Hernández, Susana Patón, Andreas Wiesbauer, Richard Gaggl, Ernesto Pun:
A 0.1 mm2, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. 2745-2754 - Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn:
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. 2755-2765 - Hyungseok Kim, Junghan Lee, Tino Copani, Seyfi S. Bazarjani, Sayfe Kiaei, Bertan Bakkaloglu:
Adaptive Blocker Rejection Continuous-Time ΔΣ ADC for Mobile WiMAX Applications. 2766-2779 - Haoyue Wang, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis:
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA. 2780-2789 - Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro:
A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-µm CMOS. 2790-2799 - Mamoru Sasaki:
A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators. 2800-2807 - Minjae Lee, Mohammad E. Heidari, Asad A. Abidi:
A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution. 2808-2816 - Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu:
Resilient Self-VDD-Tuning Scheme With Speed-Margining for Low-Power SRAM. 2817-2823 - Inge Doms, Patrick Merken, Chris Van Hoof, Robert P. Mertens:
Capacitive Power Management Circuit for Micropower Thermoelectric Generators With a 1.4 µA Controller. 2824-2833 - George Jie Yuan, Ho Yeung Chan, Sheung Wai Fung, Bing Liu:
An Activity-Triggered 95.3 dB DR -75.6 dB THD CMOS Imaging Sensor With Digital Calibration. 2834-2843 - Chao Yang, Sachin R. Jadhav, R. Mark Worden, Andrew J. Mason:
Compact Low-Power Impedance-to-Digital Converter for Sensor Array Microsystems. 2844-2855 - Filip Tavernier, Michel S. J. Steyaert:
High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS. 2856-2867 - Valentijn De Smedt, Pieter De Wit, Wim Vereecken, Michiel Steyaert:
Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001]. 2868
Volume 44, Number 11, November 2009
- Hoi-Jun Yoo, SeongHwan Cho:
Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08). 2871-2872 - Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas:
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. 2873-2880 - Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita:
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture. 2881-2890 - Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park:
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. 2891-2900 - Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz:
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. 2901-2910 - Jie-Wei Lai, Chia-Hsin Wu, Anson Lin, Wei-Kai Hong, Cheng-Yu Wang, Chih-Hsien Shen, Yu-Hsin Lin, Yi-Hsien Cho, YangChuan Chen, Yuan-Hung Chung:
A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS. 2911-2921 - Li Zhang, Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Dawn Wang, Zhihua Wang, Hongyi Chen:
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops. 2922-2934 - Bipul C. Paul, Shinobu Fujita, Masaki Okajima:
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier. 2935-2942 - Vivienne Sze, Daniel F. Finchelstein, Mahmut E. Sinangil, Anantha P. Chandrakasan:
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder. 2943-2956 - Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi:
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications. 2957-2965 - Tsan-Wen Chen, Jui-Yuan Yu, Chien-Ying Yu, Chen-Yi Lee:
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications. 2966-2976 - Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu:
Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. 2977-2986 - Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim:
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. 2987-2998 - Jerald Yoo, Seulki Lee, Hoi-Jun Yoo:
A 1.12 pJ/b Inductive Transceiver With a Fault-Tolerant Network Switch for Multi-Layer Wearable Body Area Network Applications. 2999-3010 - Koji Kotani, Atsushi Sasaki, Takashi Ito:
High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs. 3011-3018 - Sanghoon Joo, Tae-Young Choi, Byunghoo Jung:
A 2.4-GHz Resistive Feedback LNA in 0.13-µm CMOS. 3019-3029 - Denis C. Daly, Anantha P. Chandrakasan:
A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy. 3030-3038 - Ashutosh Verma, Behzad Razavi:
A 10-Bit 500-MS/s 55-mW CMOS ADC. 3039-3050 - Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, Hsin-Shu Chen:
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS. 3051-3059 - Jian-Yi Wu, Zhenyong Zhang, Raj Subramoniam, Franco Maloberti:
A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at -0.12 dB From Full Scale Input. 3060-3066 - Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara:
A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method. 3067-3078 - Jong-Phil Hong, Sang-Gug Lee:
Low Phase NoiseGm-Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO. 3079-3091 - Sang Wook Park, Edgar Sánchez-Sinencio:
RF Oscillator Based on a Passive RC Bandpass Filter. 3092-3101 - Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey, Chun-Ming Huang, Ying-Zong Juang:
An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops. 3102-3110 - Sheng-You Lin, Shen-Iuan Liu:
A 1.5 GHz All-Digital Spread-Spectrum Clock Generator. 3111-3119 - Ankur Agrawal, Andrew Liu, Pavan Kumar Hanumolu, Gu-Yeon Wei:
An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery. 3120-3130 - Pengfei Li, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah:
A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters. 3131-3145 - Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. 3146-3162 - Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan:
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. 3163-3173 - Zheng Guo, Andrew Carlson, Liang-Teck Pang, Kenneth Duong, Tsu-Jae King Liu, Borivoje Nikolic:
Large-Scale SRAM Variability Characterization in 45 nm CMOS. 3174-3192 - Matti Paavola, Mika Kämäräinen, Erkka Laulainen, Mikko Saukoski, Lauri Koskinen, Marko Kosunen, Kari A. I. Halonen:
A Micropower ΔΣ-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer. 3193-3210 - Libin Yao, Michiel S. J. Steyaert, Willy Sansen:
Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS". 3211
Volume 44, Number 12, December 2009
- Vadim Gutnik, Nikolaus Klemmer, Zhihua Wang, Michael Green, Roland Thewes:
Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference. 3227-3231 - Rong Wu, Kofi A. A. Makinwa, Johan H. Huijsing:
A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop. 3232-3243 - Hiva Hedayati, Waleed Khalil, Bertan Bakkaloglu:
A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications. 3244-3252 - Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta:
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2. 3253-3263 - Patrick P. Siniscalchi, Richard K. Hester:
A 20 W/Channel Class-D Amplifier With Near-Zero Common-Mode Radiated Emissions. 3264-3271 - Miguel Angel Rojas González, Edgar Sánchez-Sinencio:
Low-Power High-Efficiency Class D Audio Power Amplifiers. 3272-3284 - Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. 3285-3293 - Robert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, Alan MacKenzie, Tobias Hoehn, Philipp Schmitz, Heinz Werker, Andrew Glenny:
A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency. 3294-3304 - Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, Paul Wilkins:
A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC. 3305-3313 - Andrea Panigada, Ian Galton:
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction. 3314-3328 - Lane Brooks, Hae-Seung Lee:
A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC. 3329-3343 - Matthew Park, Michael H. Perrott:
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOS. 3344-3358 - Zhiyu Ru, Niels A. Moseley, Eric A. M. Klumperink, Bram Nauta:
Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference. 3359-3375 - Shouhei Kousai, Ali Hajimiri:
An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement. 3376-3392 - Debopriyo Chowdhury, Christopher D. Hull, Ofir B. Degani, Yanjie Wang, Ali M. Niknejad:
A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications. 3393-3402 - Dan Sandström, Mikko Varonen, Mikko Kärkkäinen, Kari A. I. Halonen:
W-Band CMOS Amplifiers Achieving +10 dBm Saturated Output Power and 7.5 dB NF. 3403-3409 - Munkyo Seo, Basanth Jagannathan, John J. Pekarik, Mark J. W. Rodwell:
A 150 GHz Amplifier With 8 dB Gain and +6 dBm Psat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines. 3410-3421 - Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas:
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS. 3422-3433 - Cristian Marcu, Debopriyo Chowdhury, Chintan Thakkar, Jung-Dong Park, Lingkai Kong, Maryam Tabesh, Yanjie Wang, Bagher Afshar, Abhinav Gupta, Amin Arbabian, Simone Gambini, Reza Zamani, Elad Alon, Ali M. Niknejad:
A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry. 3434-3447 - Xin He, Jan van Sinderen:
A Low-Power, Low-EVM, SAW-Less WCDMA Transmitter Using Direct Quadrature Voltage Modulation. 3448-3458 - Namjun Cho, Joonsung Bae, Hoi-Jun Yoo:
A 10.8 mW Body Channel Communication/MICS Dual-Band Transceiver for a Unified Body Sensor Network Controller. 3459-3468 - Vipul Jain, Fred Tzeng, Lei Zhou, Payam Heydari:
A Single-Chip Dual-Band 22-29-GHz/77-81-GHz BiCMOS Transceiver for Automotive Radars. 3469-3485 - Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels:
A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS. 3486-3498 - Domine Leenaerts, Remco van de Beek, Jos Bergervoet, Harish Kundur, Gerard van der Weide, Ajay Kapoor, Tian Yan Pu, Yu Fang, Yujuan Wang, Biju Joseph Mukkada, Hong Sair Lim, Madhu Kiran, Chun Swee Lim, Sorin Badiu, Alan Chang:
A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY. 3499-3510 - Francesco Gatta, Ray Gomez, Young J. Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Ertan Zencir, Frank Singor, Hans Eberhart, Loke Kun Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp:
An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0. 3511-3525 - Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman:
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. 3526-3538 - Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito:
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. 3539-3546 - Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. 3547-3559 - Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama:
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery. 3560-3567 - Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. 3568-3579 - Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. 3580-3589 - Jri Lee, Ke-Chung Wu:
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition. 3590-3602 - Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama:
A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging. 3603-3608 - Lasse Aaltonen, Kari A. I. Halonen:
Pseudo-Continuous-Time Readout Circuit for a 300°s Capacitive 2-Axis Micro-Gyroscope. 3609-3620 - Hasnain Lakdawala, Y. William Li, Arijit Raychowdhury, Greg Taylor, Krishnamurthy Soumyanath:
A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process. 3621-3630 - Peng Cong, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young:
A Wireless and Batteryless 10-Bit Implantable Blood Pressure Sensing Microsystem With Adaptive RF Powering for Real-Time Laboratory Mice Monitoring. 3631-3644 - Masoud Roham, Daniel P. Covey, David P. Daberkow, Eric S. Ramsson, Christopher D. Howard, Byron A. Heidenreich, Paul A. Garris, Pedram Mohseni:
A Wireless IC for Time-Share Chemical and Electrical Neural Recording. 3645-3658 - Yong-Joon Jeon, Hyung-Min Lee, Sungwoo Lee, Gyu-Hyeong Cho, Hyoung-Rae Kim, Yoon-Kyung Choi, Myunghee Lee:
A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs. 3659-3675
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