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ORCIDYasuo Hidaka
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2010 – 2019
- 2013
[j3]Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon:
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters. IEEE J. Solid State Circuits 48(8): 1898-1909 (2013)- [c10]Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada:
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC 2013: 28-29 - [c9]Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura:
32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. ISSCC 2013: 40-41 - 2012
- [c8]Yue Lu, Kwangmo Jung, Yasuo Hidaka, Elad Alon:
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS. CICC 2012: 1-4 - 2011
- [c7]Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker:
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC 2011: 346-348
2000 – 2009
- 2009
- [j2]Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits 44(12): 3547-3559 (2009) - [c6]Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone:
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC 2009: 188-189 - 2007
- [c5]Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone:
Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC 2007: 854-857 - [c4]Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone:
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC 2007: 442-443
1990 – 1999
- 1994
- [j1]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Architecture of parallel management kernel for PIE64. Future Gener. Comput. Syst. 10(1): 29-43 (1994) - 1993
- [c3]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Multiple Threads in Cyclic Register Windows. ISCA 1993: 131-142 - 1992
- [c2]Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka:
Architecture of Parallel Management Kernel for PIE64. PARLE 1992: 685-700 - 1991
- [c1]Yasuo Hidaka, Hanpei Koike, Jun'ichi Tatemura, Hidehiko Tanaka:
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. ISLP 1991: 470-484
Coauthor Index
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