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ORCIDKouichi Kanda
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2020 – today
- 2024
[c13]Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe:
Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs. ICCE 2024: 1-6- 2022
- [c12]Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami:
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. FPGA 2022: 155 - [c11]Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami:
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. VLSI Technology and Circuits 2022: 76-77 - 2020
- [c10]Mohammad Bagherbeik
, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami:
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems. PPSN (1) 2020: 317-331
2010 – 2019
- 2015
- [j11]Ao Ba, Maja Vidojkovic, Kouichi Kanda, Nauman F. Kiyani, Maarten Lont, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Yao-Hong Liu, Ming Ding, Benjamin Busze, Shoichi Masui, Makoto Hamaminato, Hiroyuki Sato, Kathleen Philips, Harmke de Groot:
A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications. IEEE J. Biomed. Health Informatics 19(3): 920-929 (2015) - [c9]Christian Bachmann, Maja Vidojkovic, Xiongchuan Huang, Maarten Lont, Yao-Hong Liu, Ming Ding, Benjamin Busze, Jordy Gloudemans, Hans Giesen, Adnane Sbai, Gert-Jan van Schaik, Nauman F. Kiyani, Kouichi Kanda, Kazuaki Oishi, Shoichi Masui, Kathleen Philips, Harmke de Groot:
A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS. VLSIC 2015: 94- - 2014
- [c8]Maja Vidojkovic, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Ao Ba, Maarten Lont, Yao-Hong Liu, Pieter Harpe, Ming Ding, Ben Busze, Nauman F. Kiyani, Kouichi Kanda, Shoichi Masui, Kathleen Philips, Harmke de Groot:
9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications. ISSCC 2014: 170-171 - [c7]Hans W. Pflug, Hubregt J. Visser, Nauman F. Kiyani, Guido Dolmans, Kathleen Philips, Kouichi Kanda, Makoto Hamaminato, Shoichi Masui:
Radio channel characterization for 400 MHz implanted devices. WCNC 2014: 293-298 - 2012
- [c6]Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura:
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. ISSCC 2012: 86-88 - 2011
- [j10]Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda:
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range. IEICE Trans. Electron. 94-C(6): 1049-1052 (2011) - 2010
- [j9]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010) - [c5]Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda:
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. CICC 2010: 1-4
2000 – 2009
- 2009
- [j8]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3580-3589 (2009) - [c4]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC 2009: 360-361 - 2008
- [j7]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits 43(3): 610-618 (2008) - 2007
- [j6]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. 90-C(4): 811-822 (2007) - [c3]Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone:
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC 2007: 442-443 - 2006
- [j5]Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa:
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. IEICE Trans. Electron. 89-C(3): 300-313 (2006) - [j4]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai:
Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). IEEE J. Solid State Circuits 41(4): 859-867 (2006) - 2005
- [j3]Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai:
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Trans. Electron. 88-C(4): 760-767 (2005) - [c2]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai:
Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). ISCAS (4) 2005: 3119-3122 - 2004
- [j2]Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai:
90% write power-saving SRAM using sense-amplifying memory cell. IEEE J. Solid State Circuits 39(6): 927-933 (2004) - 2001
- [j1]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE J. Solid State Circuits 36(10): 1559-1564 (2001)
1990 – 1999
- 1999
- [c1]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs. CICC 1999: 563-566
Coauthor Index
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