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2020 – today
- 2024
[j102]Dongzhu Li, Zhijie Zhan, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge, Tadahiro Kuroda:
A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. IEICE Trans. Electron. 107(6): 155-162 (2024)- [j101]Tadahiro Kuroda:
Slashing IC Power and Democratizing IC Access for the Digital Age. IPSJ Trans. Syst. LSI Des. Methodol. 17: 2-6 (2024) - [c132]Dongzhu Li, Tianqi Zhao
, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. ISCAS 2024: 1-5 - 2023
- [j100]Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. IEICE Trans. Electron. 106(7): 391-394 (2023) - [j99]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. IEEE J. Solid State Circuits 58(7): 2075-2086 (2023) - [j98]Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa:
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. IEEE Micro 43(6): 19-27 (2023) - [j97]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3440-3450 (2023) - [c131]Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. ASP-DAC 2023: 180-181 - [c130]Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. ASP-DAC 2023: 182-183 - [c129]Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. IECON 2023: 1-6 - [c128]Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. ISCAS 2023: 1-5 - [c127]Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. NEWCAS 2023: 1-4 - [c126]Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j96]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 478-486 (2022) - [j95]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. IEEE J. Solid State Circuits 57(2): 535-545 (2022) - [j94]Atsutake Kosuge, Yao-Chung Hsu, Mototsugu Hamada, Tadahiro Kuroda:
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. IEEE Open J. Circuits Syst. 3: 4-14 (2022) - [j93]Atsutake Kosuge, Tadahiro Kuroda:
Proximity Wireless Communication Technologies: An Overview and Design Guidelines. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4317-4330 (2022) - [j92]Atsutake Kosuge, Satoshi Suehiro, Mototsugu Hamada, Tadahiro Kuroda:
mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. IEEE Trans. Instrum. Meas. 71: 1-10 (2022) - [c125]Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. ASP-DAC 2022: 5-6 - [c124]Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. HCS 2022: 1-14 - [c123]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. HCS 2022: 1-14 - [c122]Saito Shibata, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. ICECS 2022 2022: 1-4 - [c121]Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Mototsugu Hamada, Tadahiro Kuroda:
A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. ICECS 2022 2022: 1-4 - [c120]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS 2022: 99-103 - [c119]Lixing Yu, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. SAS 2022: 1-6 - 2021
- [j91]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 751-761 (2021) - [j90]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 692-703 (2021) - [c118]Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. ASP-DAC 2021: 97-98 - [c117]Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. ASP-DAC 2021: 99-100 - [c116]Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. A-SSCC 2021: 1-3 - [c115]Shohei Morinaga, Tomoe Ishikawa, Masato Yasui, Mototsugu Hamada, Tadahiro Kuroda:
CA2 area detection from hippocampal microscope images using deep learning. MWSCAS 2021: 603-606 - 2020
- [c114]Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. ICECS 2020: 1-4 - [c113]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j89]Mototsugu Hamada, Tadahiro Kuroda:
Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. IEICE Trans. Electron. 102-C(7): 501-508 (2019) - [j88]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019) - [c112]Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda:
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS 2019: 1 - [c111]Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi, R. Shimizu, Hiroki Ishikuro, Tadahiro Kuroda, T. Yanagida, Ken Uchida:
Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. VLSI Circuits 2019: 158- - 2018
- [j87]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. IEICE Trans. Electron. 101-C(7): 488-492 (2018) - [j86]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - [j85]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [c110]Ryota Shimizu, Kosuke Asako, Hiroki Ojima, Shohei Morinaga, Mototsugu Hamada, Tadahiro Kuroda:
Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. AI4I 2018: 27-30 - [c109]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. ISCAS 2018: 1-4 - [c108]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC 2018: 216-218 - [c107]Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda:
Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. MWSCAS 2018: 25-28 - [c106]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. MWSCAS 2018: 1046-1049 - [c105]Yuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda:
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. VLSI Circuits 2018: 27-28 - 2017
- [c104]Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura:
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC 2017: 7-8 - [c103]Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano:
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. CANDAR 2017: 126-131 - [c102]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Wireless power transfer to stacked modules for IoT sensor nodes. ISOCC 2017: 59-60 - [c101]Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Convolutional neural network for industrial egg classification. ISOCC 2017: 67-68 - [c100]Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling link for 3-D Network-on-Chips. ISOCC 2017: 150-151 - [c99]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - 2016
- [j84]Junichiro Kadomoto, So Hasegawa, Yusuke Kiuchi, Atsutake Kosuge, Tadahiro Kuroda:
Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. IEICE Trans. Electron. 99-C(6): 659-662 (2016) - [j83]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits 51(4): 1041-1050 (2016) - [j82]Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda:
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. IEEE J. Solid State Circuits 51(6): 1446-1456 (2016) - [j81]Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 265-275 (2016) - [j80]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c98]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
Analytical thruchip inductive coupling channel design optimization. ASP-DAC 2016: 731-736 - [c97]Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. A-SSCC 2016: 41-44 - [c96]Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura:
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC 2016: 105-108 - [c95]So Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda:
A 1 Tb/s/mm2 inductive-coupling side-by-side chip link. ESSCIRC 2016: 469-472 - [c94]Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano:
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR 2016: 195-201 - [c93]Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Deep learning application trial to lung cancer diagnosis for medical sensor systems. ISOCC 2016: 191-192 - [c92]Ahmad Muzaffar bin Baharudin, Mika Saari, Pekka Sillberg, Petri Rantanen, Jari Soini, Tadahiro Kuroda:
Low-energy algorithm for self-controlled Wireless Sensor Nodes. WINCOM 2016: 42-46 - 2015
- [j79]Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda:
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. 98-C(4): 288-297 (2015) - [j78]Yasuhiro Take, Tadahiro Kuroda:
Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network. IEICE Trans. Electron. 98-C(4): 322-332 (2015) - [j77]Takahide Terada, Haruki Fukuda, Tadahiro Kuroda:
Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(4): 932-941 (2015) - [j76]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2584-2591 (2015) - [j75]Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 726-730 (2015) - [j74]Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2122-2131 (2015) - [j73]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 356-368 (2015) - [c91]Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda:
Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. ASP-DAC 2015: 44-45 - [c90]Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda:
Design and analysis for ThruChip design for manufacturing (DFM). ASP-DAC 2015: 46-47 - [c89]Atsutake Kosuge, Shu Ishizuka, Marni Abe, Satoshi Ichikawa, Tadahiro Kuroda:
24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. ISSCC 2015: 1-3 - [c88]Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda:
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. ISSCC 2015: 1-3 - [c87]Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC 2015: 82- - [c86]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC 2015: 128- - 2014
- [j72]Lechang Liu, Keisuke Ishikawa, Tadahiro Kuroda:
Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage. IEICE Trans. Electron. 97-C(6): 505-511 (2014) - [j71]Yi Zhan, Tadahiro Kuroda:
Wearable sensor-based human activity recognition from environmental background sounds. J. Ambient Intell. Humaniz. Comput. 5(1): 77-89 (2014) - [j70]Timothy C. Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs:
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. IEEE J. Solid State Circuits 49(1): 4-8 (2014) - [j69]Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits 49(1): 223-231 (2014) - [j68]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [c85]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC 2014: 31-32 - [c84]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c83]Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. ISSCC 2014: 496-497 - [c82]Yusuke Oike, Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jonathan Chang, Tadahiro Kuroda:
F2: 3D stacking technologies for image sensors and memories. ISSCC 2014: 512-513 - [c81]Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda:
A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. VLSIC 2014: 1-2 - 2013
- [j67]Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 443-452 (2013) - [j66]Tsutomu Takeya, Tadahiro Kuroda:
Symbol-Rate Clock Recovery for Integrating DFE Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(3): 705-712 (2013) - [j65]Tsutomu Takeya, Tadahiro Kuroda:
Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(5): 940-946 (2013) - [j64]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. 96-C(6): 820-827 (2013) - [j63]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. 96-D(12): 2753-2764 (2013) - [j62]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits 48(3): 790-800 (2013) - [j61]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits 48(11): 2628-2636 (2013) - [j60]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c80]Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c79]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC 2013: 91-92 - [c78]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC 2013: 111-112 - [c77]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c76]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c75]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c74]Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS 2013: 169-172 - [c73]Yuki Ono, Abdul Raziz Junaidi, Tadahiro Kuroda:
Adaptive window search using semantic texton forests for real-time object detection. ICIP 2013: 3293-3296 - [c72]Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro:
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. ISCAS 2013: 1576-1579 - [c71]Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC 2013: 200-201 - [c70]Haruki Fukuda, Takahide Terada, Tadahiro Kuroda:
Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator. ISSCC 2013: 204-205 - [c69]Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda:
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. ISSCC 2013: 214-215 - [c68]Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
3D clock distribution using vertically/horizontally-coupled resonators. ISSCC 2013: 258-259 - [c67]Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi:
F3: Emerging technologies for wireline communication. ISSCC 2013: 504-505 - [c66]Teruo Jyo, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA. RWS 2013: 217-219 - 2012
- [j59]Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda:
A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 249-256 (2012) - [j58]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. IEICE Trans. Electron. 95-C(4): 668-676 (2012) - [j57]Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. IEICE Trans. Electron. 95-C(6): 1026-1034 (2012) - [j56]Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47(4): 1022-1030 (2012) - [j55]Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda:
A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. IEEE J. Solid State Circuits 47(5): 1232-1241 (2012) - [j54]Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda:
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits 47(10): 2484-2495 (2012) - [j53]Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits 47(10): 2496-2504 (2012) - [j52]Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller. IEEE J. Solid State Circuits 47(11): 2576-2585 (2012) - [j51]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits 47(11): 2643-2653 (2012) - [j50]Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1285-1294 (2012) - [c65]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS 2012: 212-224 - [c64]Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda:
Simultaneous data and power transmission using nested clover coils. ASP-DAC 2012: 555-556 - [c63]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC 2012: 1-4 - [c62]Lechang Liu, Hiroki Ishikuro, Tadahiro Kuroda:
A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS. CICC 2012: 1-4 - [c61]Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda:
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips 2012: 1-3 - [c60]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC 2012: 381-384 - [c59]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c58]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c57]Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC 2012: 52-54 - [c56]Tadahiro Kuroda, David Ruffieux:
Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee. ISSCC 2012: 398-399 - [c55]Takayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda:
A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. ISSCC 2012: 442-444 - [c54]Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. RWS 2012: 71-74 - [c53]Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. VLSI-DAT 2012: 1-4 - 2011
- [j49]Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda:
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range. IEICE Trans. Electron. 94-C(6): 1049-1052 (2011) - [j48]Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda:
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. IEEE J. Solid State Circuits 46(4): 965-973 (2011) - [j47]Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda:
A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. IEEE J. Solid State Circuits 46(11): 2552-2559 (2011) - [j46]Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1902-1907 (2011) - [j45]Kiichi Niitsu, Vishwesh V. Kulkarni, Shinmo Kang, Hiroki Ishikuro, Tadahiro Kuroda:
A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2058-2066 (2011) - [c52]Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. A-SSCC 2011: 145-148 - [c51]Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro:
1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller. A-SSCC 2011: 177-180 - [c50]Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC 2011: 205-208 - [c49]Ryota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro:
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. ESSCIRC 2011: 471-474 - [c48]Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6W/25mm2 inductive power transfer for non-contact wafer-level testing. ISSCC 2011: 230-232 - [c47]Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda:
A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. ISSCC 2011: 490-492 - [c46]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12Gb/s non-contact interface with coupled transmission lines. ISSCC 2011: 492-494 - [c45]Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 - [c44]Tadahiro Kuroda:
ThruChip interface (TCI) for 3D networks on chip. VLSI-SoC 2011: 238-241 - [p1]Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures 2011: 225-248 - 2010
- [j44]Hiroki Ishikuro, Tadahiro Kuroda:
Wireless proximity interfaces with a pulse-based inductive coupling technique. IEEE Commun. Mag. 48(10): 192-199 (2010) - [j43]Vishal V. Kulkarni, Hiroki Ishikuro, Tadahiro Kuroda:
A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme. IEICE Trans. Electron. 93-C(1): 120-127 (2010) - [j42]Yuxiang Yuan, Yoichi Yoshida, Tadahiro Kuroda:
Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link. IEICE Trans. Electron. 93-C(2): 164-171 (2010) - [j41]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. 93-C(3): 295-302 (2010) - [j40]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2456-2462 (2010) - [j39]Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2600-2608 (2010) - [j38]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits 45(1): 134-141 (2010) - [j37]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [j36]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda:
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45(10): 2057-2065 (2010) - [j35]Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2269-2278 (2010) - [j34]Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda:
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1238-1243 (2010) - [c43]Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda:
A versatile recognition processor for sensor network applications. ASP-DAC 2010: 349-350 - [c42]Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda:
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. CICC 2010: 1-4 - [c41]Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda:
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC 2010: 1-4 - [c40]Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda:
A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. ISSCC 2010: 264-265 - [c39]Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda:
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. ISSCC 2010: 436-437 - [c38]Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda:
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. ISSCC 2010: 440-441
2000 – 2009
- 2009
- [j33]Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda:
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna. IEEE J. Solid State Circuits 44(2): 394-403 (2009) - [j32]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits 44(3): 947-955 (2009) - [j31]Yuichi Hori, Yuya Hanai, Jun Nishimura, Tadahiro Kuroda:
Architecture Design of Versatile Recognition Processor for Sensornet Applications. IEEE Micro 29(6): 44-57 (2009) - [j30]Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai:
A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(11): 2511-2518 (2009) - [c37]Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda:
A wireless real-time on-chip bus trace system. ASP-DAC 2009: 91-92 - [c36]Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda:
A 1 GHz CMOS comparator with dynamic offset control technique. ASP-DAC 2009: 103-104 - [c35]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC 2009: 279-282 - [c34]Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC 2009: 449-452 - [c33]Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano:
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 - [c32]Yuya Hanai, Tadahiro Kuroda:
Face detection through compact classifier using Adaptive Look-Up-Table. ICIP 2009: 1225-1228 - [c31]Yuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda:
A versatile recognition processor employing Haar-like feature and cascaded classifier. ISSCC 2009: 148-149 - [c30]Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC 2009: 244-245 - [c29]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno:
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471 - [c28]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2008
- [j29]Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. 91-C(2): 200-205 (2008) - [j28]Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits 43(1): 285-291 (2008) - [j27]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. IEEE J. Solid State Circuits 43(3): 610-618 (2008) - [j26]Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda:
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. IEEE J. Solid State Circuits 43(11): 2363-2369 (2008) - [c27]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A dynamic offset control technique for comparator design in scaled CMOS technology. CICC 2008: 495-498 - [c26]Jun Nishimura, Nobuo Sato, Tadahiro Kuroda:
Speaker Siglet Detection for Business Microscope. ICMLA 2008: 376-381 - [c25]Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai:
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. ISSCC 2008: 292-293 - [c24]Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC 2008: 298-299 - [c23]Jun Nishimura, Tadahiro Kuroda:
Eating habits monitoring using wireless wearable in-ear microphone. ISWPC 2008: 130-132 - [c22]Jun Nishimura, Nobuo Sato, Tadahiro Kuroda:
Speech "Siglet" Detection for Business Microscope (concise contribution). PerCom 2008: 147-152 - 2007
- [j25]Tadahiro Kuroda:
Special Section on Low-Power, High-Speed LSIs and Related Technologies. IEICE Trans. Electron. 90-C(4): 655-656 (2007) - [j24]Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
18-GHz Clock Distribution Using a Coupled VCO Array. IEICE Trans. Electron. 90-C(4): 811-822 (2007) - [j23]Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda:
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. 90-C(4): 829-835 (2007) - [j22]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42(1): 111-122 (2007) - [j21]Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits 42(2): 410-421 (2007) - [j20]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. IEEE J. Solid State Circuits 42(3): 627-636 (2007) - [j19]Yuichi Hori, Tadahiro Kuroda:
A 0.79-mm2 29-mW Real-Time Face Detection Core. IEEE J. Solid State Circuits 42(4): 790-797 (2007) - [j18]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42(12): 2726-2735 (2007) - [c21]Noriyuki Miura, Tadahiro Kuroda:
A 1Tb/s 3W Inductive-Coupling Transceiver Chip. ASP-DAC 2007: 92-93 - [c20]Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda:
Wideband Inductive-coupling Interface for High-performance Portable System. CICC 2007: 13-20 - [c19]Vishal V. Kulkarni, Muhammad Muqsith, Hiroki Ishikuro, Tadahiro Kuroda:
A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter. CICC 2007: 647-650 - [c18]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC 2007: 224-598 - [c17]Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC 2007: 358-608 - [c16]Hiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda:
An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. ISSCC 2007: 360-608 - 2006
- [j17]Tadahiro Kuroda:
System LSI: Challenges and Opportunities. IEICE Trans. Electron. 89-C(3): 213-220 (2006) - [j16]Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda:
A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. 89-C(3): 320-326 (2006) - [j15]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda:
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits 41(1): 23-34 (2006) - [j14]Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Tadahiro Kuroda:
A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding. IEEE J. Solid State Circuits 41(4): 891-898 (2006) - [c15]Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai:
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC 2006: 575-578 - [c14]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC 2006: 1676-1685 - [c13]Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. ISSCC 2006: 2102-2111 - [c12]Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda:
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. VLSI Design 2006: 271-276 - 2005
- [j13]Bruce Gieseke, Tadahiro Kuroda:
Introduction to the Special Issue. IEEE J. Solid State Circuits 40(4): 811-812 (2005) - [j12]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits 40(4): 829-837 (2005) - [j11]Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda:
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. IEEE J. Solid State Circuits 40(4): 986-993 (2005) - [j10]Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005) - 2004
- [c11]Noriyuki Miura, Naoki Kato, Tadahiro Kuroda:
Practical methodology of post-layout gate sizing for 15% more power saving. ASP-DAC 2004: 434-437 - [c10]Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda:
Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC 2004: 99-102 - [c9]Yuichi Hori, Kenji Shimizu, Yutaka Nakamura, Tadahiro Kuroda:
A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template. ICPR (1) 2004: 765-768 - [c8]Takahide Terada, Shingo Yoshizumi, Yukitoshi Sanada, Tadahiro Kuroda:
Transceiver circuits for pulse-based ultra-wideband. ISCAS (4) 2004: 349-352 - 2002
- [c7]Tadahiro Kuroda:
Optimization and control of VDD and VTH for low-power, high-speed CMOS design. ICCAD 2002: 28-34 - [c6]Tadahiro Kuroda:
Low-Power, High-Speed CMOS VLSI Design. ICCD 2002: 310-315 - 2001
- [j9]Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda:
A bitline leakage compensation scheme for low-voltage SRAMs. IEEE J. Solid State Circuits 36(5): 726-734 (2001) - [c5]Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda:
Utilizing surplus timing for power reduction. CICC 2001: 89-92 - 2000
- [j8]Tadahiro Kuroda, Mototsugu Hamada:
Low-power CMOS digital design with dual embedded adaptive power supplies. IEEE J. Solid State Circuits 35(4): 652-655 (2000) - [j7]Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama:
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid State Circuits 35(11): 1713-1721 (2000)
1990 – 1999
- 1999
- [c4]Fuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru Furuyama:
Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec. ISLPED 1999: 54-59 - 1998
- [j6]Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama:
Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits 33(3): 454-462 (1998) - [j5]Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama:
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33(11): 1772-1780 (1998) - [c3]Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda:
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC 1998: 495-498 - [c2]Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda:
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488 - 1996
- [j4]Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray:
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits 31(6): 819-827 (1996) - [j3]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai:
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE J. Solid State Circuits 31(11): 1770-1779 (1996) - [j2]Tadahiro Kuroda, Takayasu Sakurai:
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. J. VLSI Signal Process. 13(2-3): 191-201 (1996) - [c1]Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai:
Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED 1996: 309-312 - 1994
- [j1]Tadahiro Kuroda, Yoshinori Sakata, Kenji Matsuo:
Analysis and optimization of BiCMOS gate circuits. IEEE J. Solid State Circuits 29(5): 564-571 (1994)
Coauthor Index
[j102] [c132] [j100] [j99] [j98] [j97] [c131] [c130] [c129] [c128] [c127] [c126] [j96] [j95] [j94] [j92] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [j91] [j90] [c118] [c117] [c116] [c115] [c114] [c113] [j89] [j88] [c112] [j87] [c110] [c109] [c108] [c107] [c106] [c105] [c102] [c101] [c93] [c5] [j8] [j7] [j5] [c3] [c2]
[c111] [j83] [j81] [j74] [j73] [c86] [j69] [c85] [c83] [j67] [j64] [j62] [j61] [c79] [c78] [c72] [c71] [c68] [c66] [j58] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [c63] [c62] [c60] [c57] [c55] [c54] [j46] [j45] [c52] [c51] [c50] [c49] [c48] [c46] [j44] [j43] [j38] [j35] [j34] [c40] [j33] [j32] [c37] [c34] [c30] [j29] [j28] [c24] [c20] [c19] [c17] [c16]
Junichiro Kadomoto
aka: Junichiro Kadamoto
aka: Junichiro Kadamoto
[j69] [j62] [j60] [c79] [c77] [c76] [c75] [c71] [c69] [c68] [j59] [j58] [j54] [j53] [j51] [j50] [c64] [c63] [c61] [c58] [c57] [j48] [j47] [c50] [c48] [c47] [c46] [j38] [j35] [c39] [c38] [j32] [c34] [c33] [c30] [j29] [j28] [j26] [c24] [j23] [j22] [j21] [c21] [c20] [c17] [j16] [j15] [c14] [c12] [j12] [c11] [c10]
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