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ORCIDIchiro Fujimori
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2010 – 2019
- 2017
[j12]Fazil Ahmad
, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. IEEE J. Solid State Circuits 52(1): 21-32 (2017)- [c13]Yohan Frans, Ichiro Fujimori, Seung-Jun Bae, Samuel Palermo, Hideyuki Nosaka, Simone Erba:
F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. ISSCC 2017: 512-514 - [c12]Ichiro Fujimori, Pavan Kumar Hanumolu:
EE4: Semiconductor economics: How business decisions are engineered. ISSCC 2017: 523 - 2016
- [c11]Hui Pan, Junhua Tan, Evelyn Wenting Wang, Jingguang Wang, Karthik Swaminathan, Ramalingam Pandarinathan, Ramesh Pasagadugula, VamshiKrishna Yakkala, Mostafa Hammad, Karim Abdelhalim, Kaijun Li, Su Cui, Jing Wang, Ahmad Chini, Mehmet Tazebay, Suresh Venkatesan, Derek Tam, Ichiro Fujimori, Kambiz Vakilian:
10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS. ISSCC 2016: 186-187 - [c10]Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. ISSCC 2016: 324-325 - [c9]Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka:
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC 2016: 502-505 - 2015
- [j11]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. IEEE J. Solid State Circuits 50(4): 856-866 (2015) - [j10]Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Mohammed M. Abdul-Latif, Kambiz Vakilian, Ichiro Fujimori, Anthony Brewster:
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS. IEEE J. Solid State Circuits 50(12): 3089-3100 (2015) - [c8]Stephane Le Tuai, Borivoje Nikolic, Tetsuya Iizuka, Ichiro Fujimori:
F1: High-speed interleaved ADCs. ISSCC 2015: 1-2 - 2014
- [j9]Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Derek Tam, Ichiro Fujimori:
A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 3141-3155 (2014) - [c7]Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Jenny Yu, Joseph N. Y. Aziz, Derek Tam, Ichiro Fujimori:
8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS. ISSCC 2014: 148-149 - [c6]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. VLSIC 2014: 1-2 - 2013
- [c5]Ichiro Fujimori, Masafumi Nogawa:
Session 7 overview: Optical transceivers and silicon photonics. ISSCC 2013: 114-115 - [c4]Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi:
F3: Emerging technologies for wireline communication. ISSCC 2013: 504-505 - 2012
- [c3]Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John T. Stonick:
Optical PCB interconnects, Niche or mainstream? ISSCC 2012: 516 - 2011
- [c2]Hui Pan, Magesh Valliappan, Wei Zhang, Kambiz Vakilian, Seong-Ho Lee, Hamid Hatamkhani, Mario Caresosa, Karo Khanoyan, Haitao Tong, Duke Tran, Anthony Brewster, Ichiro Fujimori:
A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS. ISSCC 2011: 442-444 - 2010
- [j8]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. IEEE J. Solid State Circuits 45(6): 1172-1185 (2010)
2000 – 2009
- 2009
- [c1]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. ISSCC 2009: 370-371 - 2007
- [j7]Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori:
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS. IEEE J. Solid State Circuits 42(4): 872-880 (2007) - 2002
- [j6]Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian:
OC-192 transmitter and receiver in standard 0.18-μm CMOS. IEEE J. Solid State Circuits 37(12): 1768-1780 (2002) - 2001
- [j5]Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai:
A fully integrated SONET OC-48 transceiver in standard CMOS. IEEE J. Solid State Circuits 36(12): 1964-1973 (2001) - 2000
- [j4]Ichiro Fujimori, Akihiko Nogi, Tetsuro Sugimoto:
A multibit delta-sigma audio DAC with 120-dB dynamic range. IEEE J. Solid State Circuits 35(8): 1066-1073 (2000) - [j3]Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan:
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio. IEEE J. Solid State Circuits 35(12): 1820-1828 (2000)
1990 – 1999
- 1998
- [j2]Ichiro Fujimori, Tetsuro Sugimoto:
A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter. IEEE J. Solid State Circuits 33(12): 1863-1870 (1998) - 1997
- [j1]Ichiro Fujimori, Kazuo Koyama, David Trager, Fred Tam, Lorenzo Longo:
A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range. IEEE J. Solid State Circuits 32(3): 329-336 (1997)
Coauthor Index
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