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"19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ..."
Fazil Ahmad et al. (2016)
- Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. ISSCC 2016: 324-325
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