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2010 – 2019
- 2018
[c8]Chi-Hung Lin, Jackie Koon Lun Wong, Tae-Youn Kim, Guangxi Ray Xie, Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie G. Venes:
A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS. ISSCC 2018: 360-362- 2017
- [j4]Fazil Ahmad
, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. IEEE J. Solid State Circuits 52(1): 21-32 (2017) - 2016
- [j3]Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez:
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. IEEE J. Solid State Circuits 51(4): 845-859 (2016) - [c7]Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori:
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. ISSCC 2016: 324-325 - [c6]Jiangfeng Wu, Acer Wei-Te Chou, Tianwei Li, Rong Wu, Tao Wang, Giuseppe Cusmai, Sha-Ting Lin, Cheng-Hsun Yang, Greg Unruh, Sunny Raj Dommaraju, Mo M. Zhang, Po Tang Yang, Wei-Ting Lin, Xi Chen, Dongsoo Koh, Qingqi Dou, Hemasundar Mohan Geddada, Juo-Jung Hung, Massimo Brandolini, Young Shin, Hung Sen Huang, Chun-Ying Chen, Ardie G. Venes:
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS. ISSCC 2016: 466-467 - [c5]Jianhong Xiao, Weinan Gao, Xiaojing Xu, Dave S.-H. Chang, Jiang Cao, Runhua Sun, Vijay Periasamy, Ning-Yi Wang, Xi Chen, Greg Unruh, Takayuki Hayashi, Tai-Hong Chih, Lakshminarasimhan Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, Bo Shen, Ardie G. Venes, Dongsoo Koh, James Y. C. Chang:
A 180 mW multistandard TV tuner in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j2]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. IEEE J. Solid State Circuits 50(4): 856-866 (2015) - [j1]Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Bryan Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Yuan Yao, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen:
A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS. IEEE J. Solid State Circuits 50(12): 2922-2934 (2015) - [c4]Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen:
26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS. ISSCC 2015: 1-3 - [c3]Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez:
A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver. VLSIC 2015: 214- - 2014
- [c2]Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. VLSIC 2014: 1-2 - 2011
- [c1]Siavash Fallahi, Delong Cui, Deyi Pi, Rose Zhu, Greg Unruh, Marcel Lugthart, Afshin Momtaz:
A 19 mW/lane Serdes transceiver for SFI-5.1 application. CICC 2011: 1-4
Coauthor Index
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