"A 5.184Gbps/ch through-chip interface and automated place-and-route design ..."

Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda (2012)

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DOI: 10.1109/COOLCHIPS.2012.6216583

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda:
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips 2012: 1-3

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