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ORCIDRyuichi Sakamoto
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2020 – today
- 2024
[c24]Toshio Endo, Shohei Minami, Akihiro Nomura, Hiroki Ohtsuji, Jun Kato, Masahiro Miwa, Eiji Yoshida, Tomoya Yuki, Ryuichi Sakamoto:
Challenges in Computing Resource Sharing Towards Next-Gen Interactive Accelerated HPC. ISC Workshops 2024: 231-242- 2023
- [j7]Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto:
Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems. Int. J. Netw. Comput. 13(1): 48-61 (2023) - [j6]Siyi Hu
, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura:
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocess. Microsystems 102: 104895 (2023) - [c23]Ryo Ouchi, Ryuichi Sakamoto:
Extendable MQTT Broker for Feedback-based Resource Management in Large-scale Computing Environments. APNet 2023: 190-191 - 2022
- [c22]Ryuichi Sakamoto, Yuriko Ezaki, Masaaki Kondo:
Hash Distributed A* on an FPGA. HEART 2022: 76-83 - [c21]Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto:
Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems. IPDPS Workshops 2022: 445-448 - [c20]Siyi Hu, Masaaki Kondo, Yuan He, Ryuichi Sakamoto, Hao Zhang, Jun Zhou, Hiroshi Nakamura:
GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. PDP 2022: 135-143 - 2021
- [j5]Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Guanqin Pan, Thang Cao, Masaaki Kondo:
Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems. IEICE Trans. Electron. 104-C(6): 237-246 (2021) - [j4]Ryuichi Sakamoto:
Lexicographic and reverse lexicographic quadratic Gröbner bases of cut ideals. J. Symb. Comput. 103: 201-212 (2021) - [c19]Yuta Suzuki, Ryuichi Sakamoto, Hiroshi Nakamura:
Dynamic Power Management for 5G Small Cell Base Station. COMSNETS 2021: 492-500 - [c18]Yunjiao Ma, Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Masaaki Kondo:
Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL. CANDAR (Workshops) 2021: 94-100 - 2020
- [c17]Ryuichi Sakamoto, Masaaki Kondo, Kohei Fujita, Tsuyoshi Ichimura, Kengo Nakajima:
The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption. HPC Asia 2020: 199-206 - [c16]Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo:
Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. ITSC 2020: 1-8
2010 – 2019
- 2019
- [c15]Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki:
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - [i1]Kentaro Fukamizu, Masaaki Kondo, Ryuichi Sakamoto:
Generation High resolution 3D model from natural language by Generative Adversarial Network. CoRR abs/1901.07165 (2019) - 2018
- [c14]Ryuichi Sakamoto, Tapasya Patki, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Daniel A. Ellsworth, Barry Rountree, Martin Schulz:
Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers. IPDPS 2018: 526-535 - [c13]Atsushi Koshiba, Ryuichi Sakamoto, Mitaro Namiki:
OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators. RTCSA 2018: 236-237 - 2017
- [c12]Ryuichi Sakamoto, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Tapasya Patki, Daniel A. Ellsworth, Barry Rountree, Martin Schulz:
Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework. IPDPS 2017: 957-966 - [c11]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC 2017: 155-156 - [c10]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC 2017: 13-20 - 2016
- [j3]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - 2015
- [j2]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - 2014
- [c9]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c8]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - 2013
- [j1]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c7]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c6]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c5]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - 2012
- [c4]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c3]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c2]Mikiko Sato, Go Fukazawa, Kiyohiko Nagamine, Ryuichi Sakamoto, Mitaro Namiki, Kazumi Yoshinaga, Yuichi Tsujita, Atsushi Hori, Yutaka Ishikawa:
A design of hybrid operating system for a parallel computer with multi-core and many-core processors. ROSS@ICS 2012: 9:1-9:8 - [c1]Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki:
An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422
Coauthor Index
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