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2020 – today
- 2024
[j70]Taisei Saito, Kota Ando, Tetsuya Asai
:
Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights. IEICE Trans. Inf. Syst. 107(8): 949-957 (2024)- [j69]Yuki Abe, Kohei Nishida, Kota Ando, Tetsuya Asai:
SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA. Int. J. Parallel Emergent Distributed Syst. 39(2): 197-213 (2024) - [c66]Itsuki Akeno, Hiiro Yamazaki, Tetsuya Asai, Kota Ando:
Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer. IJCNN 2024: 1-8 - [c65]Koki Minagawa, Taisei Saito, Sena Kojima, Kota Ando, Tetsuya Asai:
Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference. IJCNN 2024: 1-8 - 2022
- [j68]Yoshiharu Yamagishi, Tatsuya Kaneko, Megumi Akai-Kasaya, Tetsuya Asai:
Holmes: A Hardware-Oriented Optimizer Using Logarithms. IEICE Trans. Inf. Syst. 105-D(12): 2040-2047 (2022) - [j67]Megumi Akai-Kasaya, Yuki Takeshima, Shaohua Kan, Kohei Nakajima, Takahide Oya, Tetsuya Asai:
Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate. Neuromorph. Comput. Eng. 2(1): 14003 (2022) - [j66]Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32(5): 2666-2686 (2022) - 2020
- [j65]Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda:
A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. 10(2): 84-93 (2020) - [j64]Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai:
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3015-3028 (2020)
2010 – 2019
- 2019
- [j63]Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. 102-D(12): 2295-2305 (2019) - [j62]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. 102-D(12): 2341-2353 (2019) - [c64]Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
DeltaNet: Differential Binary Neural Network. ASAP 2019: 39 - [c63]Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA 2019: 1-8 - [c62]Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR 2019: 137-142 - [c61]Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai:
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. ReConFig 2019: 1-8 - [p2]Tetsuya Asai:
Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors. Handbook of Memristor Networks 2019: 1229-1239 - 2018
- [j61]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018: 3618621:1-3618621:11 (2018) - [j60]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [j59]Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano:
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61: 21-31 (2018) - [c60]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT 2018: 6-13 - [c59]Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai:
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP 2018: 1842-1846 - [c58]Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC 2018: 237-243 - [c57]Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP 2018: 1-4 - 2017
- [j58]Takahide Oya, Tetsuya Asai:
Special issue of emerging stochastic computing and hardware. Int. J. Parallel Emergent Distributed Syst. 32(3): 243 (2017) - [j57]Makoto Takano, Tetsuya Asai, Takahide Oya:
Design and evaluation of single-electron associative memory circuit. Int. J. Parallel Emergent Distributed Syst. 32(3): 259-270 (2017) - [j56]Enrico Prati, Ernesto Giussani, Giorgio Ferrari, Tetsuya Asai:
Noise-assisted transmission of spikes in Maeda-Makino artificial neuron arrays. Int. J. Parallel Emergent Distributed Syst. 32(3): 278-286 (2017) - [j55]Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani:
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 462-466 (2017) - [c56]Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
Accelerating deep learning by binarized hardware. APSIPA 2017: 1045-1051 - [c55]Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura:
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC 2017: 7-8 - [c54]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL 2017: 1 - [c53]Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A Time-Division Multiplexing Ising Machine on FPGAs. HEART 2017: 3:1-3:6 - [c52]Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR 2017: 291-297 - [c51]Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN 2017: 2510-2516 - [c50]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid:
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS 2017: 1 - [c49]Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura:
Low latency divider using ensemble of moving average curves. ISQED 2017: 397-402 - [c48]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - [c47]Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. 2017: 137-142 - 2016
- [j54]Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura:
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. 12(2-3): 169-187 (2016) - [c46]Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS 2016: 297-300 - [c45]Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura:
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC 2016: 105-108 - [c44]Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid:
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS 2016: 357-360 - [c43]Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig 2016: 1-6 - [c42]Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig 2016: 1-6 - 2015
- [j53]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura:
Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. 23(2): 143-152 (2015) - [j52]Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 726-730 (2015) - [c41]Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC 2015: 82- - 2014
- [j51]Lizeth Gonzalez-Carabarin, Tetsuya Asai, Masato Motomura:
Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express 11(15): 20140632 (2014) - [c40]Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura:
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC 2014: 37-40 - [c39]Hiroyuki Otake, Kazuyoshi Ishimura, Tetsuya Asai, Takahide Oya:
Signal Amplification by Circular Single-Electron Oscillator Network with Stochastic Resonance. BICT 2014 - [c38]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura:
Caching memcached at reconfigurable network interface. FPL 2014: 1-6 - [c37]Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura:
Achieving higher performance of memcached by caching at network interface. FPT 2014: 288-289 - 2013
- [c36]Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura:
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC 2013: 220 - [c35]Kazuki Nakada, Keiji Miura, Tetsuya Asai:
Dynamical system design for silicon neurons using phase reduction approach. EMBC 2013: 4997-5000 - [c34]Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS 2013: 169-172 - [c33]Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura:
Exploiting hardware reconfigurability on window join. HPCS 2013: 690-691 - [c32]Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura:
A restricted dynamically reconfigurable architecture for low power processors. ReConFig 2013: 1-7 - 2012
- [c31]Kazuki Nakada, Keiji Miura, Tetsuya Asai, Hisa-Aki Tanaka:
Dynamical systems design of nonlinear oscillators using phase reduction approach. APCCAS 2012: 308-311 - [c30]Kazuki Nakada, Keiji Miura, Tetsuya Asai:
Silicon neuron design based on phase reduction analysis. SCIS&ISIS 2012: 1059-1062 - 2011
- [j50]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. 7(1-2): 53-63 (2011) - 2010
- [j49]Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya:
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express 7(19): 1467-1473 (2010) - [j48]Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. 93-C(6): 741-746 (2010) - [j47]Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. 93-C(6): 835-841 (2010) - [j46]Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya:
A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. 19(4): 763-772 (2010) - [j45]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 681-685 (2010) - [c29]Tetsuya Asai, Yuzuru Ohba, Kiyoshi Ohishi, Katsuyuki Majima, Shiro Urushihara, Koichi Kageyama:
High performance sensor-less injection force control considering friction phenomenon. AMC 2010: 30-35 - [c28]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya:
Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) 2010: 188-195
2000 – 2009
- 2009
- [j44]Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 436-442 (2009) - [j43]Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya:
Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2508-2513 (2009) - [j42]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3079-3081 (2009) - [j41]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici:
A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. Int. J. Nanotechnol. Mol. Comput. 1(2): 80-92 (2009) - [j40]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits 44(7): 2047-2054 (2009) - [j39]Yuzuru Ohba, Masaki Sazawa, Kiyoshi Ohishi, Tetsuya Asai, Katsuyuki Majima, Yukio Yoshizawa, Koichi Kageyama:
Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon. IEEE Trans. Ind. Electron. 56(8): 2955-2960 (2009) - [c27]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96 - [c26]Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC 2009: 392-395 - [c25]Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya:
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS 2009: 140-143 - [c24]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) 2009: 384-391 - [c23]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya:
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN 2009: 1600-1605 - [c22]Ken Ueno, Tetsuya Asai, Yoshihito Amemiya:
Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS 2009: 5-8 - [c21]Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose:
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS 2009: 1565-1568 - [c20]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya:
Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet 2009: 51-56 - [p1]Tetsuya Asai, Takahide Oya:
Nature-inspired Single-electron Computers. Artificial Life Models in Hardware 2009: 133-159 - [r1]Tetsuya Asai:
Unconventional Computing, Novel Hardware for. Encyclopedia of Complexity and Systems Science 2009: 9706-9726 - 2008
- [j38]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express 5(6): 204-210 (2008) - [j37]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2475-2481 (2008) - [j36]Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. 4(1): 45-59 (2008) - [c19]Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Katsumi Tateno, Hatsuo Hayashi, Yoshitaka Ohtubo, Tsutomu Miki, Kiyonori Yoshii:
Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array. CSE 2008: 307-312 - [c18]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC 2008: 398-401 - [c17]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya:
Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) 2008: 851-858 - 2007
- [j35]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2108-2115 (2007) - [j34]Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos 17(5): 1713-1719 (2007) - [j33]Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya:
Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos 17(10): 3613-3617 (2007) - [j32]Takahide Oya, Ikuko N. Motoike, Tetsuya Asai:
Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata. Int. J. Bifurc. Chaos 17(10): 3651-3655 (2007) - [j31]Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya:
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007) - [j30]Youhei Suzuki, Takahiro Takayama, Ikuko N. Motoike, Tetsuya Asai:
Striped and Spotted Pattern Generation on Reaction-diffusion Cellular Automata - Theory and LSI Implementation. Int. J. Unconv. Comput. 3(1): 1-13 (2007) - [j29]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya:
A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. 3(4): 271-284 (2007) - [j28]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits 42(4): 798-803 (2007) - [j27]Andrew Adamatzky, Christof Teuscher, Tetsuya Asai:
Editorial. Int. J. Parallel Emergent Distributed Syst. 22(2): 77-78 (2007) - [c16]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126 - [c15]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901 - [c14]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751 - 2006
- [j26]Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya:
Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express 3(13): 292-298 (2006) - [j25]Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express 3(22): 464-468 (2006) - [j24]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 902-907 (2006) - [j23]Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya:
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos 16(1): 207-212 (2006) - [j22]Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi:
Analog Vlsi Implementation of Resonate-and-fire Neuron. Int. J. Neural Syst. 16(6): 445-456 (2006) - [c13]Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi:
Burst Synchronization in Two Pulse-Coupled Resonate-and-Fire Neuron Circuits. IFIP PPAI 2006: 285-294 - [c12]Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Hatsuo Hayashi:
Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron. ISCAS 2006: 5183-5186 - 2005
- [b1]Andrew Adamatzky, Ben de Lacy Costello, Tetsuya Asai:
Reaction-diffusion computers. Elsevier 2005, ISBN 978-0-444-52042-5, pp. I-XIV, 1-334 - [j21]Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya:
On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express 2(3): 76-80 (2005) - [j20]Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya:
Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. 88-C(6): 1142-1147 (2005) - [j19]Tetsuya Asai, Ben de Lacy Costello, Andrew Adamatzky:
Silicon Implementation of a Chemical Reaction-diffusion Processor for Computation of Voronoi Diagram. Int. J. Bifurc. Chaos 15(10): 3307-3320 (2005) - [j18]Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya:
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. 1(2): 123-147 (2005) - [j17]Takahide Oya, Tetsuya Asai, Takashi Fukui, Yoshihito Amemiya:
Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. Int. J. Unconv. Comput. 1(2): 179-196 (2005) - [j16]Masayuki Ikebe, Tetsuya Asai:
A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA. J. Robotics Mechatronics 17(4): 372-377 (2005) - [j15]Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya:
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005) - [j14]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1095-1103 (2005) - [c11]Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Analog current-mode CMOS implementation of central pattern generator for robot locomotion. IJCNN 2005: 639-644 - [c10]Takahide Oya, Tetsuya Asai, Ryo Kagaya, Yoshihito Amemiya:
Noise performance of single-electron depressing synapses for neuronal synchrony detection. IJCNN 2005: 2849-2854 - [c9]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) 2005: 1923-1926 - [c8]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici:
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538 - 2004
- [j13]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Design of an Artificial Central Pattern Generator with Feedback Controller. Intell. Autom. Soft Comput. 10(2): 185-192 (2004) - [j12]Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express 1(4): 73-76 (2004) - [j11]Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya:
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express 1(9): 248-252 (2004) - [j10]Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya:
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. 19(4) (2004) - [j9]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. J. Robotics Mechatronics 16(4): 397-403 (2004) - [c7]Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya:
A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. IJCNN 2004: 2619-2624 - [c6]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) 2004: 1-4 - 2003
- [j8]Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya:
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics 15(2): 208-218 (2003) - [j7]Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya:
A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks 14(5): 1308-1312 (2003) - [j6]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Trans. Neural Networks 14(5): 1356-1365 (2003) - [c5]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya:
An analog neural oscillator circuit for locomotion controller in quadruped walking robot. IJCNN 2003: 983-988 - [c4]Tetsuya Asai, Yoshihito Amemiya:
Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL 2003: 197-206 - 2002
- [j5]Tetsuya Asai, Yuusaku Nishimiya, Yoshihito Amemiya:
A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(9): 2093-2096 (2002) - [c3]Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya:
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC 2002: 6 - 2000
- [j4]Tetsuya Asai, Shinji Hara, Tetsuya Iwasaki:
Simultaneous parametric uncertainty modeling and robust control synthesis by LFT scaling. Autom. 36(10): 1457-1467 (2000) - [c2]Tetsuya Asai, Masato Koutani, Yoshihito Amemiya:
An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) 2000: 494-499
1990 – 1999
- 1999
- [j3]Tetsuya Asai, Tomoki Fukai, Shigeru Tanaka:
A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution. Neural Networks 12(2): 211-216 (1999) - [j2]Tetsuya Asai, Masashiro Ohtani, Hiroo Yonezu:
Analog integrated circuits for the Lotka-Volterra competitive neural networks. IEEE Trans. Neural Networks 10(5): 1222-1231 (1999) - 1998
- [c1]Hiroo Yonezu, Tetsuya Asai, Masahiro Ohtani, Jang-Kyoo Shin, Naoki Ohshima:
An analog integrated circuit for motion detection. KES (3) 1998: 506-509 - 1996
- [j1]Tetsuya Asai, Hideyo Yokotsuka, Tomoki Fukai:
A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities. IEEE Trans. Neural Networks 7(1): 182-189 (1996)
Coauthor Index
[j50] [j49] [j48] [j47] [j46] [j45] [c28] [j44] [j43] [j42] [j40] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [j38] [j37] [j36] [c18] [c17] [j35] [j34] [j33] [j31] [j29] [j28] [c16] [c15] [c14] [j26] [j25] [j24] [j23] [j21] [j20] [j18] [j17] [j15] [j14] [c11] [c10] [c9] [c8] [j13] [j12] [j11] [j10] [j9] [c7] [c6] [j8] [j7] [j6] [c5] [c4] [j5] [c3] [c2]
Shinya Takamaeda-Yamazaki
aka: Shinya Takamaeda
aka: Shinya Takamaeda
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