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ORCIDMicroprocessors and Microsystems, Volume 61
Volume 61, September 2018
- Karyofyllis Patsidis
, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. 1-10
- Emad Ebeid, Martin Skriver, Kristian Husum Terkildsen, Kjeld Jensen, Ulrik Pagh Schultz:
A survey of Open-Source UAV flight controllers and flight simulators. 11-20
- Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano:
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. 21-31 - Eleftherios Lygouras, Antonios Gasteratos, Konstantinos Tarchanidis, Athanasios C. Mitropoulos:
ROLFER: A fully autonomous aerial rescue support system. 32-42
- Robert Hülle, Petr Fiser, Jan Schmidt:
ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. 43-57
- Manolis Katevenis, Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose Antonio Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Bernd Lietzow, Martin L. Kersten:
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. 58-71 - Gamil A. Ahmed, Muhammad E. S. Elrabaa:
FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems. 72-85 - Wasif Afzal, Hugo Bruneliere, Davide Di Ruscio, Andrey Sadovykh, Silvia Mazzini, Eric Cariou, Dragos Truscan, Jordi Cabot, Abel Gómez, Jesús Gorroñogoitia, Luigi Pomante, Pavel Smrz:
The MegaM@Rt2 ECSEL project: MegaModelling at Runtime - Scalable model-based framework for continuous development and runtime validation of complex systems. 86-95 - Mário P. Véstias, Horácio C. Neto:
Improving the area of fast parallel decimal multipliers. 96-107
- Macarena C. Martínez-Rodríguez, Piedad Brox, Iluminada Baturone:
A comparative analysis of VLSI trusted virtual sensors. 108-116 - Lampros Pyrgas, Paris Kitsos, Athanassios Skodras:
Compact FPGA architectures for the two-band fast discrete Hartley transform. 117-125 - Maricela Jiménez Rodríguez, M. E. Cano, Octavio Flores Siordia, Juan Carlos Estrada Gutiérrez:
A portable embedded system for point-to-point secure signals transmission. 126-134 - Asma Benmessaoud Gabis, Pierre Bomel, Marc Sevaux:
Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip. 135-153
- José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni:
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. 154-170
- Emanuele Torti, Alessandro Fontanella, Giordana Florimbi, Francesco Leporati, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó:
Acceleration of brain cancer detection algorithms during surgery procedures using GPUs. 171-178
- Ching-Han Chen, Leh Luoh, Min-Hao Guo:
A new design and implementation of hardware accelerator for line detection. 179-197
- Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø:
Using dynamic partial reconfiguration of FPGAs in real-Time systems. 198-206 - Yuanhong Huo, Dake Liu:
High-throughput bit processor for cryptography, error correction, and error detection. 207-216 - Zohre Beiki, Z. Zare Dorabi, Ali Jahanian:
Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation. 217-226 - Anissa Sghaier, Zeghid Medien, Loubna Ghammam, Sylvain Duquesne, Mohsen Machhout, Hassan Yousif Ahmed:
High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA. 227-241
- Seungbum Jo, Markus Lohrey, Damian Ludwig, Simon Meckel, Roman Obermaisser, Simon Plasger:
An architecture for online-diagnosis systems supporting compressed communication. 242-256 - Sundararaman Rajagopalan, Sivaraman R, Har Narayan Upadhyay, John Bosco Balaguru Rayappan, Rengarajan Amirtharajan:
ON-Chip peripherals are ON for chaos - an image fused encryption. 257-278
- Ramiro Sámano-Robles, Júlio C. Viana, Nelson Ferreira, João Loureiro, Joao Cintra, André Rocha, Eduardo Tovar:
Active flow control using dense wireless sensor and actuator networks. 279-295 - Qaisar Bashir, Muhammad Naeem Shehzad, Muhammad Naeem Awais, Umer Farooq, Mirza Tariq Hamayun, Irfan Ali:
A scheduling based energy-aware core switching technique to avoid thermal threshold values in multi-core processing systems. 296-305 - Laurence Crestani Tasca, Edison Pignaton de Freitas, Flávio Rech Wagner:
Enhanced architecture for programmable logic controllers targeting performance improvements. 306-315
- Florian Neugebauer, Ilia Polian, John P. Hayes:
S-box-based random number generation for stochastic computing. 316-326
- Saeid Zoka, Mohammad Gholami:
A novel rising Edge Triggered Resettable D flip-flop using five input majority gate. 327-335 - Li Li, Fenghua Li, Kui Geng, Guozhen Shi:
Design of Multi Cipher Processing Architecture for Random Cross Access. 336-343
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