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ORCIDShinya Takamaeda-Yamazaki
Shinya Takamaeda
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2020 – today
- 2024
[j20]Tatsuya Kubo
, Shinya Takamaeda-Yamazaki:
Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems. IEEE Micro 44(1): 38-48 (2024)- [c45]Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. ASPDAC 2024: 539-544 - [c44]Kotaro Shimamura, Shinya Takamaeda-Yamazaki:
FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees. CCNC 2024: 839-842 - [i6]Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. CoRR abs/2408.16246 (2024) - 2023
- [j19]Peiqi Zhang, Shinya Takamaeda-Yamazaki:
MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network Hardware. IEICE Trans. Inf. Syst. 106(12): 2006-2014 (2023) - [c43]Masayuki Usui, Shinya Takamaeda-Yamazaki:
High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. ARC 2023: 3-18 - [c42]Masayoshi Tsutsui, Shinya Takamaeda-Yamazaki:
SPinS-FL: Communication-Efficient Federated Subnetwork Learning. CCNC 2023: 605-610 - [c41]Tatsuya Kubo, Shinya Takamaeda-Yamazaki:
Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory. COOL CHIPS 2023: 1-6 - [c40]Sun Tanaka, Shinya Takamaeda-Yamazaki:
MAO: Memory Architecture Obfuscation. MCSoC 2023: 233-240 - [c39]Yuki Hirayama, Kengo Suga, Shinya Takamaeda-Yamazaki:
GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation. MCSoC 2023: 522-529 - [c38]Masayoshi Tsutsui, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki:
Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack. UbiSec 2023: 191-204 - [i5]Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. CoRR abs/2308.15040 (2023) - [i4]Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling. CoRR abs/2312.06086 (2023) - 2022
- [j18]Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32(5): 2666-2686 (2022) - [c37]Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. FPT 2022: 1-9 - [c36]Sefutsu Ryu, Shinya Takamaeda-Yamazaki:
Model-based Federated Reinforcement Distillation. GLOBECOM 2022: 1109-1114 - [c35]Keisuke Kamahori, Shinya Takamaeda-Yamazaki:
Accelerating Decision Tree Ensemble with Guided Branch Approximation. HEART 2022: 24-32 - [c34]Peiqi Zhang, Shinya Takamaeda-Yamazaki:
Multi-Input Adaptive Activation Function for Binary Neural Networks. CANDARW 2022: 90-96 - [i3]Yuki Hirayama, Shinya Takamaeda-Yamazaki:
MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity. CoRR abs/2211.13402 (2022) - [i2]Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. CoRR abs/2212.00357 (2022) - 2021
- [j17]Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura:
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access 9: 6179-6187 (2021) - [j16]Shinya Takamaeda:
Foreword. IEICE Trans. Inf. Syst. 104-D(12): 2028 (2021) - [j15]Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56(1): 165-178 (2021) - [j14]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 692-703 (2021) - [c33]Yoshiki Fujiwara, Shinya Takamaeda-Yamazaki:
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design. ASAP 2021: 226-233 - [c32]Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. FPL 2021: 167-173 - [i1]Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. CoRR abs/2110.07186 (2021) - 2020
- [j13]Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda:
A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. 10(2): 84-93 (2020) - [j12]Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai:
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3015-3028 (2020) - [c31]Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki:
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC 2020: 345-357 - [c30]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS 2020: 1-5 - [c29]Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC 2020: 138-140
2010 – 2019
- 2019
- [j11]Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. 102-D(12): 2295-2305 (2019) - [j10]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. 102-D(12): 2341-2353 (2019) - [j9]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019) - [c28]Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
DeltaNet: Differential Binary Neural Network. ASAP 2019: 39 - [c27]Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA 2019: 1-8 - [c26]Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR 2019: 137-142 - 2018
- [j8]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018: 3618621:1-3618621:11 (2018) - [j7]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. 101-D(2): 288-302 (2018) - [j6]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [j5]Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano:
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61: 21-31 (2018) - [c25]Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT 2018: 6-13 - [c24]Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai:
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP 2018: 1842-1846 - [c23]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC 2018: 216-218 - [c22]Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC 2018: 237-243 - [c21]Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe:
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP 2018: 1-4 - 2017
- [c20]Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
Accelerating deep learning by binarized hardware. APSIPA 2017: 1045-1051 - [c19]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM 2017: 192 - [c18]Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai:
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL 2017: 1 - [c17]Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
A Time-Division Multiplexing Ising Machine on FPGAs. HEART 2017: 3:1-3:6 - [c16]Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura:
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR 2017: 291-297 - [c15]Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119 - [c14]Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. 2017: 137-142 - 2016
- [j4]Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
Performance Optimization of Light-Field Applications on GPU. IEICE Trans. Inf. Syst. 99-D(12): 3072-3081 (2016) - [c13]Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR 2016: 57-66 - [c12]Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR 2016: 361-367 - [c11]Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR 2016: 375-380 - 2015
- [j3]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. 98-D(12): 2141-2149 (2015) - [j2]Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise:
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. IEICE Trans. Inf. Syst. 98-D(12): 2150-2158 (2015) - [c10]Shinya Takamaeda-Yamazaki:
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. ARC 2015: 451-460 - [c9]Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. CANDAR 2015: 385-391 - [c8]Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC 2015: 73-80 - 2014
- [c7]Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise:
Ultrasmall: The smallest MIPS soft processor. FPL 2014: 1-4 - [c6]Shinya Takamaeda-Yamazaki, Kenji Kise:
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. FPL 2014: 1-4 - [c5]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR 2014: 388-393 - [c4]Shinya Takamaeda-Yamazaki, Kenji Kise:
A framework for efficient rapid prototyping by virtually enlarging FPGA resources. ReConFig 2014: 1-8 - 2012
- [c3]Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise:
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC 2012: 138-150 - [c2]Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise:
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. ICNC 2012: 343-349 - 2011
- [j1]Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise:
An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News 39(4): 38-43 (2011) - 2010
- [c1]Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise:
Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC 2010: 133-139
Coauthor Index
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