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2020 – today
- 2024
[j2]Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura:
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024)- [c14]Yung-Chin Chen
, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. ASPDAC 2024: 539-544 - [i4]Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura:
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR abs/2402.14029 (2024) - 2023
- [c13]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. IISWC 2023: 15-27 - [c12]Daichi Fujiki:
MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory. MICRO 2023: 800-814 - [i3]Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. CoRR abs/2308.15040 (2023) - [i2]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. CoRR abs/2309.02680 (2023) - [i1]Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling. CoRR abs/2312.06086 (2023) - 2022
- [c11]Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das:
Multi-Layer In-Memory Processing. MICRO 2022: 920-936 - 2021
- [b1]Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das:
In-/Near-Memory Computing. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2021, ISBN 978-3-031-00644-9, pp. 1-140 - [j1]Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw:
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. IEEE J. Solid State Circuits 56(3): 824-833 (2021) - 2020
- [c10]Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw:
A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. CICC 2020: 1-4 - [c9]Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das:
SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. MICRO 2020: 937-950
2010 – 2019
- 2019
- [c8]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
Duality cache for data parallel acceleration. ISCA 2019: 397-410 - [c7]Daichi Fujiki, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor:
Near-memory data transformation for efficient sparse matrix multi-vector multiplication. SC 2019: 55:1-55:17 - 2018
- [c6]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
In-Memory Data Parallel Processor. ASPLOS 2018: 1-14 - [c5]Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy:
GenAx: A Genome Sequencing Accelerator. ISCA 2018: 69-82 - [c4]Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS 2018: 6:1-6:8 - 2017
- [c3]Daichi Fujiki, Scott A. Mahlke, Reetuparna Das:
In-memory Data Flow Processor. PACT 2017: 375 - [c2]Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi:
High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA 2017: 469-480 - 2016
- [c1]Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP 2016: 168-175
Coauthor Index
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last updated on 2024-10-07 22:18 CEST by the dblp team
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