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ORCIDNishil Talati
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2020 – today
- 2024
[j6]Kuan-Yu Chen
, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw:
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication. ACM Trans. Reconfigurable Technol. Syst. 17(4): 61:1-61:32 (2024)- [c17]Yuchen Xia, Jiho Kim, Yuhan Chen, Haojie Ye, Souvik Kundu, Cong Callie Hao, Nishil Talati:
Understanding the Performance and Estimating the Cost of LLM Fine-Tuning. IISWC 2024: 210-223 - [c16]Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal:
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms. ISCA 2024: 597-612 - [i7]Yuchen Xia, Jiho Kim, Yuhan Chen, Haojie Ye, Souvik Kundu, Cong Hao, Nishil Talati:
Understanding the Performance and Estimating the Cost of LLM Fine-Tuning. CoRR abs/2408.04693 (2024) - [i6]Yunjie Pan, Omkar Bhalerao, C. Seshadhri, Nishil Talati:
Accurate and Fast Estimation of Temporal Motifs using Path Sampling. CoRR abs/2409.08975 (2024) - [i5]Haojie Ye, Yuchen Xia, Yuhan Chen, Kuan-Yu Chen, Yichao Yuan, Shuwen Deng, Baris Kasikci, Trevor N. Mudge, Nishil Talati:
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design. CoRR abs/2411.05400 (2024) - 2023
- [j5]Yichao Yuan, Haojie Ye, Sanketh Vedula, Wynn Kaza, Nishil Talati:
Everest: GPU-Accelerated System For Mining Temporal Motifs. Proc. VLDB Endow. 17(2): 162-174 (2023) - [j4]Yuhan Chen, Haojie Ye, Sanketh Vedula, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati:
Demystifying Graph Sparsification Algorithms in Graph Properties Preservation. Proc. VLDB Endow. 17(3): 427-440 (2023) - [c15]Haojie Ye, Sanketh Vedula, Yuhan Chen, Yichen Yang, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati:
GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference. ASPLOS (3) 2023: 282-301 - [c14]Yuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan, Trevor N. Mudge:
PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows. DATE 2023: 1-6 - [c13]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. IISWC 2023: 15-27 - [c12]Heewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati:
RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models. ISLPED 2023: 1-6 - [i4]Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski:
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher. CoRR abs/2301.12312 (2023) - [i3]Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das:
Vector-Processing for Mobile Devices: Benchmark and Analysis. CoRR abs/2309.02680 (2023) - [i2]Yichao Yuan, Haojie Ye, Sanketh Vedula, Wynn Kaza, Nishil Talati:
Everest: GPU-Accelerated System For Mining Temporal Motifs. CoRR abs/2310.02800 (2023) - [i1]Yuhan Chen, Haojie Ye, Sanketh Vedula, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati:
Demystifying Graph Sparsification Algorithms in Graph Properties Preservation. CoRR abs/2311.12314 (2023) - 2022
- [c11]Leul Belayneh, Haojie Ye, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati:
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems. PACT 2022: 304-316 - [c10]Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski:
NDMiner: accelerating graph pattern mining using near data processing. ISCA 2022: 146-159 - [c9]Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski:
Mint: An Accelerator For Mining Temporal Motifs. MICRO 2022: 1270-1287 - 2021
- [j3]Heewoo Kim, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, Ronald G. Dreslinski:
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors. ACM J. Emerg. Technol. Comput. Syst. 17(3): 27:1-27:44 (2021) - [c8]Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi, Todd M. Austin, Michael F. P. O'Boyle, Scott A. Mahlke, Trevor N. Mudge, Ronald G. Dreslinski:
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design. HPCA 2021: 654-667 - [c7]Nishil Talati, Di Jin, Haojie Ye, Ajay Brahmakshatriya, Ganesh S. Dasika, Saman P. Amarasinghe, Trevor N. Mudge, Danai Koutra, Ronald G. Dreslinski:
A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning. IISWC 2021: 87-100 - 2020
- [c6]Yichen Yang, Haojie Ye, Yuhan Chen, Xueyang Liu, Nishil Talati, Xin He, Trevor N. Mudge, Ronald G. Dreslinski:
CoPTA: Contiguous Pattern Speculating TLB Architecture. SAMOS 2020: 67-83
2010 – 2019
- 2019
- [j2]Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39(1): 33-43 (2019) - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - 2018
- [c5]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - 2017
- [c4]Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky:
Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. ICCAD 2017: 225-232 - [c3]Nishil Talati, Zhiying Wang, Shahar Kvatinsky:
Rate-compatible and high-throughput architecture designs for encoding LDPC codes. ISCAS 2017: 1-4 - [c2]John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2015
- [j1]Pravin Mane, Nishil Talati, Ameya Riswadkar, Ramesh Raghu, C. K. Ramesha:
Stateful-NOR based reconfigurable architecture for logic implementation. Microelectron. J. 46(6): 551-562 (2015) - [c1]Pravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani, C. K. Ramesha:
Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture. VLSID 2015: 523-528
Coauthor Index
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