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ORCIDTodd M. Austin
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- affiliation: University of Michigan, Ann Arbor, USA
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2020 – today
- 2024
[c112]Venkat Nitin Patnala, Sai Manoj Pudukotai Dinakarrao, Guru Venkataramani, Jie Chen, Preet Derasari, Milos Doroslovacki, Fan Yao, Hongyu Fang, Meron Demissie, Todd M. Austin, Lauren Biernacki, Saket Upadhyay, Arnabjyoti Kalita, Ashish Venkat:
Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions. CASES 2024: 5-14- [c111]Biniyam Mengist Tiruye, Lauren Biernacki, Tersiteab Adem, Petros Mola, Todd M. Austin:
Octal: Efficient Automatic Data-Oblivious Program Transformations to Eliminate Side-Channel Leakage. SecDev 2024: 129-139 - [c110]Donayam Benti, Todd M. Austin:
Channelizer: Explainable ML Inference for Validating Side-Channel Resistant Systems. SEED 2024: 23-34 - 2023
- [c109]Qinhan Tan
, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin:
Security Verification of Low-Trust Architectures. CCS 2023: 945-959 - [c108]Lauren Biernacki, Biniyam Mengist Tiruye, Meron Zerihun Demissie, Fitsum Assamnew Andargie, Brandon Reagen, Todd M. Austin:
Exploring the Efficiency of Data-Oblivious Programs. ISPASS 2023: 189-200 - [i4]Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin:
Security Verification of Low-Trust Architectures. CoRR abs/2309.00181 (2023) - 2022
- [c107]Nicholas Wendt, Todd M. Austin, Valeria Bertacco:
PriMax: maximizing DSL application performance with selective primitive acceleration. DAC 2022: 139-144 - [c106]Shibo Chen, Yonathan Fisseha, Jean-Baptiste Jeannin, Todd M. Austin:
Twine: A Chisel Extension for Component-Level Heterogeneous Design. DATE 2022: 466-471 - [c105]Tarunesh Verma, Achilleas Anastasopoulos, Todd M. Austin:
These Aren't The Caches You're Looking For: Stochastic Channels on Randomized Caches. SEED 2022: 37-48 - [c104]Lauren Biernacki, Meron Zerihun Demissie, Kidus Birkayehu Workneh, Fitsum Assamnew Andargie, Todd M. Austin:
Sequestered Encryption: A Hardware Technique for Comprehensive Data Privacy. SEED 2022: 73-84 - 2021
- [j26]Lauren Biernacki, Mark Gallagher, Zhixing Xu, Misiker Tadesse Aga, Austin Harris, Shijia Wei, Mohit Tiwari, Baris Kasikci, Sharad Malik, Todd M. Austin:
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. ACM J. Emerg. Technol. Comput. Syst. 17(3): 42:1-42:38 (2021) - [c103]Austin Harris, Tarunesh Verma, Shijia Wei, Lauren Biernacki, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd M. Austin:
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HOST 2021: 226-238 - [c102]Todd M. Austin, Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari:
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. HCS 2021: 1-18 - [c101]Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi, Todd M. Austin, Michael F. P. O'Boyle, Scott A. Mahlke, Trevor N. Mudge, Ronald G. Dreslinski:
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design. HPCA 2021: 654-667 - [c100]Pete Ehrett, Todd M. Austin, Valeria Bertacco:
Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets. ICCD 2021: 395-399 - [c99]Pete Ehrett, Nathan Block, Bing Schaefer, Adrian Berding, John Paul Koenig, Pranav Srinivasan, Valeria Bertacco, Todd M. Austin:
A Defense-Inspired Benchmark Suite. ISPASS 2021: 79-80 - [c98]Hiwot Tadese Kassa, Tarunesh Verma, Todd M. Austin, Valeria Bertacco:
ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems. ISQED 2021: 292-299 - [c97]Lauren Biernacki, Meron Zerihun Demissie, Kidus Birkayehu Workneh, Galane Basha Namomsa, Plato Gebremedhin, Fitsum Assamnew Andargie, Brandon Reagen, Todd M. Austin:
VIP-Bench: A Benchmark Suite for Evaluating Privacy-Enhanced Computation Frameworks. SEED 2021: 139-149 - 2020
- [c96]Lauren Biernacki, Mark Gallagher, Valeria Bertacco, Todd M. Austin:
Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces. HOST 2020: 57-68
2010 – 2019
- 2019
- [c95]Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin:
Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS 2019: 469-484 - [c94]Misiker Tadesse Aga, Todd M. Austin:
Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization. CGO 2019: 26-36 - [c93]Pete Ehrett, Todd M. Austin, Valeria Bertacco:
SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design. DATE 2019: 510-515 - [c92]Misiker Tadesse Aga, Colton Holoday, Todd M. Austin:
Wrangling in the Power of Code Pointers with ProxyCFI. DBSec 2019: 317-337 - [c91]Austin Harris, Shijia Wei, Prateek Sahu, Pranav Kumar, Todd M. Austin, Mohit Tiwari:
Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference. MICRO 2019: 57-72 - [e1]Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis:
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 561, Springer 2019, ISBN 978-3-030-23424-9 [contents] - [i3]Salessawi Ferede Yitbarek, Todd M. Austin:
Neverland: Lightweight Hardware Extensions for Enforcing Operating System Integrity. CoRR abs/1905.05975 (2019) - 2018
- [c90]Salessawi Ferede Yitbarek, Todd M. Austin:
Reducing the overhead of authenticated memory encryption using delta encoding and ECC memory. DAC 2018: 35:1-35:6 - [c89]Zelalem Birhanu Aweke, Todd M. Austin:
uSFI: Ultra-lightweight software fault isolation for IoT-class devices. DATE 2018: 1015-1020 - [c88]Zelalem Birhanu Aweke, Todd M. Austin:
Øzone: Efficient execution with zero timing leakage for modern microarchitectures. DATE 2018: 1123-1128 - [c87]Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari:
Vulnerability-tolerant secure architectures. ICCAD 2018: 46 - [c86]Timothy Linscott, Pete Ehrett, Valeria Bertacco, Todd M. Austin:
SWAN: mitigating hardware trojans with design ambiguity. ICCAD 2018: 91 - 2017
- [j25]Kaiyuan Yang, Matthew Hicks, Qing Dong, Todd M. Austin, Dennis Sylvester:
Exploiting the analog properties of digital circuits for malicious hardware. Commun. ACM 60(9): 83-91 (2017) - [c85]Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco:
Energy efficient object detection on the mobile GP-GPU. AFRICON 2017: 945-950 - [c84]Misiker Tadesse Aga, Zelalem Birhanu Aweke, Todd M. Austin:
When good protections go bad: Exploiting anti-DoS measures to accelerate rowhammer attacks. HOST 2017: 8-13 - [c83]Zelalem Birhanu Aweke, Todd M. Austin:
Øzone: Efficient execution with zero timing leakage for modern microarchitectures. HOST 2017: 153 - [c82]Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin:
Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. HPCA 2017: 313-324 - [c81]Ofir Weisse, Valeria Bertacco, Todd M. Austin:
Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves. ISCA 2017: 81-93 - [c80]Todd M. Austin:
Keynote: Peering into the post Moore's Law world. ISLPED 2017: 1 - [c79]Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, Todd M. Austin, Valeria Bertacco:
SNIFFER: A high-accuracy malware detector for enterprise-based systems. IVSW 2017: 70-75 - [i2]Zelalem Birhanu Aweke, Todd M. Austin:
Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures. CoRR abs/1703.07706 (2017) - 2016
- [j24]Mohit Tiwari, Todd M. Austin:
On Architectural Support for Systems Security. IEEE Micro 36(5): 6-7 (2016) - [c78]Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd M. Austin:
ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. ASPLOS 2016: 743-755 - [c77]Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin:
Exploring specialized near-memory processing for data intensive operations. DATE 2016: 1449-1452 - [c76]Kaiyuan Yang, Matthew Hicks, Qing Dong, Todd M. Austin, Dennis Sylvester:
A2: Analog Malicious Hardware. IEEE Symposium on Security and Privacy 2016: 18-37 - 2015
- [c75]William Arthur, Ben Mehne, Reetuparna Das, Todd M. Austin:
Getting in control of your control flow with control-data isolation. CGO 2015: 79-90 - [c74]Todd M. Austin:
Keynote talk I: Ending the Tyranny of Amdahl's Law. ICCD 2015: vii-ix - [c73]William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin:
Locking down insecure indirection with hardware-based control-data isolation. MICRO 2015: 115-127 - [c72]Todd M. Austin:
Bridging the Moore's Law Performance Gap with Innovation Scaling. ICPE 2015: 1 - 2013
- [c71]Jason Clemons, Andrea Pellegrini, Silvio Savarese, Todd M. Austin:
EVA: An efficient vision architecture for mobile systems. CASES 2013: 13:1-13:10 - [c70]William Arthur, Biruk Mammo, Ricardo Rodríguez Jorge, Todd M. Austin, Valeria Bertacco:
Schnauzer: scalable profiling for likely security bug sites. CGO 2013: 24:1-24:11 - 2012
- [c69]Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd M. Austin:
A case for unlimited watchpoints. ASPLOS 2012: 159-172 - [c68]Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco:
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. DATE 2012: 1106-1109 - [c67]Jason Clemons, Sid Ying-Ze Bao, Silvio Savarese, Todd M. Austin, Vinay Sharma:
MVSS: Michigan Visual Sonification System. ESPA 2012: 143-146 - 2011
- [c66]Joseph L. Greathouse, Chelsea LeBlanc, Todd M. Austin, Valeria Bertacco:
Highly scalable distributed dataflow analysis. CGO 2011: 277-288 - [c65]Jason Clemons, Andrew Jones, Robert Perricone, Silvio Savarese, Todd M. Austin:
EFFEX: an embedded processor for computer vision based feature extraction. DAC 2011: 1020-1025 - [c64]Jason Clemons, Haishan Zhu, Silvio Savarese, Todd M. Austin:
MEVBench: A mobile computer vision benchmarking suite. IISWC 2011: 91-102 - [c63]Joseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd M. Austin:
Demand-driven software race detection using hardware performance counters. ISCA 2011: 165-176 - [c62]Joseph L. Greathouse, Todd M. Austin:
The potential of sampling for dynamic analysis. PLAS 2011: 3 - 2010
- [c61]Kypros Constantinides, Todd M. Austin:
Using introspective software-based testing for post-silicon debug and repair. DAC 2010: 537-542 - [c60]Daniel Gajski, Todd M. Austin, Steve Svoboda:
What input-language is the best choice for high level synthesis (HLS)? DAC 2010: 857-858 - [c59]Andrea Pellegrini, Valeria Bertacco, Todd M. Austin:
Fault-based attack of RSA authentication. DATE 2010: 855-860
2000 – 2009
- 2009
- [j23]Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco:
A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers 58(8): 1063-1079 (2009) - [j22]Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David T. Blaauw:
Energy-Efficient Subthreshold Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1127-1137 (2009) - 2008
- [j21]Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao:
Reliable Systems on Unreliable Fabrics. IEEE Des. Test Comput. 25(4): 322-332 (2008) - [j20]Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd M. Austin, Dennis Sylvester, David T. Blaauw:
Exploring Variability and Performance in a Sub-200-mV Processor. IEEE J. Solid State Circuits 43(4): 881-891 (2008) - [j19]Mojtaba Mehrara, Todd M. Austin:
Exploiting selective placement for low-cost memory protection. ACM Trans. Archit. Code Optim. 5(3): 14:1-14:24 (2008) - [j18]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 380-393 (2008) - [c58]Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin:
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. ICCD 2008: 363-370 - [c57]Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin:
Polymorphic On-Chip Networks. ISCA 2008: 101-112 - [c56]Todd M. Austin:
On the rules of low-power design (and how to break them). ISLPED 2008: 381-382 - [c55]Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling. MICRO 2008: 117-128 - [c54]Kypros Constantinides, Onur Mutlu, Todd M. Austin:
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. MICRO 2008: 282-293 - 2007
- [j17]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky:
Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. 4(1): 2 (2007) - [j16]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1126-1138 (2007) - [c53]Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin:
Low-cost protection for SER upsets and silicon defects. DATE 2007: 1146-1151 - [c52]Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin:
Architectural implications of brick and mortar silicon manufacturing. ISCA 2007: 244-253 - [c51]Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco:
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108 - [i1]Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction. CoRR abs/0710.4679 (2007) - 2006
- [j15]Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circuits 41(4): 792-804 (2006) - [c50]Mojtaba Mehrara, Todd M. Austin:
Reliability-aware data placement for partial memory protection in embedded processors. Memory System Performance and Correctness 2006: 11-18 - [c49]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Depth-driven verification of simultaneous interfaces. ASP-DAC 2006: 442-447 - [c48]Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin:
Ultra low-cost defect protection for microprocessor pipelines. ASPLOS 2006: 73-82 - [c47]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Shielding against design flaws with field repairable control logic. DAC 2006: 344-347 - [c46]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky:
BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16 - [c45]Todd M. Austin:
Robust low power computing in the nanoscale era. SBCCI 2006: 6 - [c44]Todd M. Austin:
Razor: a low-power pipeline based on circuit-level timing speculation. SBCCI 2006: 13 - 2005
- [c43]Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge:
Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7 - [c42]Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw:
A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256 - [c41]Ilya Wagner, Valeria Bertacco, Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors. DAC 2005: 783-788 - [c40]Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85 - [c39]Todd M. Austin, Valeria Bertacco:
Deployment of Better Than Worst-Case Design: Solutions and Needs. ICCD 2005: 550-558 - [c38]Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David T. Blaauw:
Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207 - [c37]David Roberts, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner:
Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70 - 2004
- [j14]Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner:
Making Typical Silicon Matter with Razor. Computer 37(3): 57-65 (2004) - [j13]Todd M. Austin, David T. Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne H. Wolf:
Mobile Supercomputers. Computer 37(5): 81-83 (2004) - [j12]Dan Ernst, Shidhartha Das, Seokwoo Lee, David T. Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner:
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004) - [j11]Doug Burger, Todd M. Austin, Stephen W. Keckler:
Recent extensions to the SimpleScalar tool suite. SIGMETRICS Perform. Evaluation Rev. 31(4): 4-7 (2004) - [c36]Rajeev Krishna, Scott A. Mahlke, Todd M. Austin:
Memory system design space exploration for low-power, real-time speech recognition. CODES+ISSS 2004: 140-145 - [c35]Todd M. Austin:
Designing robust microarchitectures. DAC 2004: 78 - [c34]Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Circuit-aware architectural simulation. DAC 2004: 305-310 - [c33]Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors. ISLPED 2004: 212-217 - [c32]Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge:
Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324 - 2003
- [j10]Nam Sung Kim, Todd M. Austin, David T. Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan:
Leakage Current: Moore's Law Meets Static Power. Computer 36(12): 68-75 (2003) - [j9]Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
Measuring Architectural Vulnerability Factors. IEEE Micro 23(6): 70-75 (2003) - [c31]Rajeev Krishna, Scott A. Mahlke, Todd M. Austin:
Architectural optimizations for low-power, real-time speech recognition. CASES 2003: 220-231 - [c30]Dan Ernst, Andrew Hamel, Todd M. Austin:
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. ISCA 2003: 253-262 - [c29]Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18 - [c28]Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO 2003: 29-42 - [c27]Eric Larson, Todd M. Austin:
High Coverage Detection of Input-Related Security Faults. USENIX Security Symposium 2003 - 2002
- [j8]Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson:
Performance Simulation Tools. Computer 35(2): 38-39 (2002) - [j7]Todd M. Austin, Eric Larson, Dan Ernst:
SimpleScalar: An Infrastructure for Computer System Modeling. Computer 35(2): 59-67 (2002) - [c26]Dan Ernst, Todd M. Austin:
Efficient Dynamic Scheduling Through Tag Elimination. ISCA 2002: 37-46 - [c25]Glenn Reinman, Brad Calder, Todd M. Austin:
High Performance and Energy Efficient Serial Prefetch Architecture. ISHPC 2002: 146-159 - [c24]Christopher T. Weaver, Eric Larson, Todd M. Austin:
Effective support of simulation in computer architecture instruction. WCAE 2002: 9 - 2001
- [j6]Todd M. Austin:
Design for Verification? IEEE Des. Test Comput. 18(4): 80, 77 (2001) - [j5]Glenn Reinman, Brad Calder, Todd M. Austin:
Optimizations Enabled by a Decoupled Front-End Architecture. IEEE Trans. Computers 50(4): 338-355 (2001) - [c23]Christopher T. Weaver, Rajeev Krishna, Lisa Wu, Todd M. Austin:
Application specific architectures: a recipe for fast, flexible and power efficient designs. CASES 2001: 181-185 - [c22]Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin:
Scalable Hybrid Verification of Complex Microprocessors. DAC 2001: 41-46 - [c21]Christopher T. Weaver, Todd M. Austin:
A Fault Tolerant Approach to Microprocessor Design. DSN 2001: 411-420 - [c20]Lisa Wu, Christopher T. Weaver, Todd M. Austin:
CryptoManiac: a fast flexible architecture for secure communication. ISCA 2001: 110-119 - [c19]Eric Larson, Saugata Chatterjee, Todd M. Austin:
MASE: a novel infrastructure for detailed microarchitectural modeling. ISPASS 2001: 1-9 - [c18]Christopher T. Weaver, Kenneth C. Barr, Eric D. Marsman, Dan Ernst, Todd M. Austin:
Performance analysis using pipeline visualization. ISPASS 2001: 18-21 - 2000
- [j4]Todd M. Austin:
DIVA: A Dynamic Approach to Microprocessor Verification. J. Instr. Level Parallelism 2 (2000) - [c17]Jerome Burke, John McDonald, Todd M. Austin:
Architectural Support for Fast Symmetric-Key Cryptography. ASPLOS 2000: 178-189 - [c16]Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin:
Efficient checker processor design. MICRO 2000: 87-97 - [c15]Eric Larson, Todd M. Austin:
Compiler controlled value prediction using branch predictor based confidence. MICRO 2000: 327-336
1990 – 1999
- 1999
- [j3]Gary S. Tyson, Todd M. Austin:
Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. Int. J. Parallel Program. 27(5): 357-380 (1999) - [j2]Pradip Bose, Thomas M. Conte, Todd M. Austin:
Challenges in processor modeling and validation [Guest Editors?? introduction]. IEEE Micro 19(3): 9-14 (1999) - [c14]Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin:
Classifying load and store instructions for memory renaming. International Conference on Supercomputing 1999: 399-407 - [c13]Glenn Reinman, Todd M. Austin, Brad Calder:
A Scalable Front-End Architecture for Fast Instruction Delivery. ISCA 1999: 234-245 - [c12]Glenn Reinman, Brad Calder, Todd M. Austin:
Fetch Directed Instruction Prefetching. MICRO 1999: 16-27 - [c11]Todd M. Austin:
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. MICRO 1999: 196-207 - 1998
- [c10]Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad Calder:
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures. IEEE PACT 1998: 278-285 - [c9]Brad Calder, Chandra Krintz, Simmi John, Todd M. Austin:
Cache-Conscious Data Placement. ASPLOS 1998: 139-149 - [c8]Todd M. Austin:
The SimpleScalar tool set as an instructional tool: experiences and future directions. WCAE@HPCA 1998: 1 - 1997
- [j1]Doug Burger, Todd M. Austin:
The SimpleScalar tool set, version 2.0. SIGARCH Comput. Archit. News 25(3): 13-25 (1997) - [c7]Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin:
On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56 - [c6]Gary S. Tyson, Todd M. Austin:
Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO 1997: 218-227 - 1996
- [b1]Todd M. Austin:
Hardware and software mechanisms for reducing load latency. University of Wisconsin-Madison, WI, USA, Technical Report / University of Wisconsin, Madison / Computer Sciences Department 1311, 1996, pp. I-VIII, 1-145 - [c5]Todd M. Austin, Gurindar S. Sohi:
High-Bandwidth Address Translation for Multiple-Issue Processors. ISCA 1996: 158-167 - 1995
- [c4]Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi:
Streamlining Data Cache Access with Fast Address Calculation. ISCA 1995: 369-380 - [c3]Todd M. Austin, Gurindar S. Sohi:
Zero-cycle loads: microarchitecture support for reducing load latency. MICRO 1995: 82-92 - 1994
- [c2]Todd M. Austin, Scott E. Breach, Gurindar S. Sohi:
Efficient Detection of All Pointer and Array Access Errors. PLDI 1994: 290-301 - 1992
- [c1]Todd M. Austin, Gurindar S. Sohi:
Dynamic Dependency Analysis of Ordinary Programs. ISCA 1992: 342-351
Coauthor Index
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