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ORCIDGurindar S. Sohi
Guri Sohi
Person information
- affiliation: University of Wisconsin-Madison, Madison, WI, USA
- award (2011): Eckert-Mauchly Award
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2020 – today
- 2024
[i2]Shyam Murthy, Gurindar S. Sohi:
Instruction Block Movement with Coupled High-Level Program Sequencing. CoRR abs/2406.06738 (2024)- [i1]Shyam Murthy, Gurindar S. Sohi:
A Non-Traditional Approach to Assisting Data Address Translation. CoRR abs/2408.15878 (2024) - 2022
- [j26]Alisa Scherer
, Guri Sohi:
Special Issue on Hot Chips 33. IEEE Micro 42(3): 6 (2022) - 2021
- [c82]Vanshika Baoni, Adarsh Mittal, Gurindar S. Sohi:
Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses. MICRO 2021: 366-379
2010 – 2019
- 2018
- [c81]Hongil Yoon, Jason Lowe-Power, Gurindar S. Sohi:
Filtering Translation Bandwidth with Virtual Caching. ASPLOS 2018: 113-127 - 2017
- [c80]Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi:
ATM: Approximate Task Memoization in the Runtime System. IPDPS 2017: 1140-1150 - 2016
- [c79]Hongil Yoon, Gurindar S. Sohi:
Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. HPCA 2016: 212-224 - 2015
- [j25]Samuel Naffziger, Guri Sohi:
Hot Chips 26 [Guest editors' introduction]. IEEE Micro 35(2): 4-5 (2015) - 2014
- [c78]Samuel Naffziger, Guri Sohi:
Welcome program chairs. Hot Chips Symposium 2014: 1-2 - [c77]Jichuan Chang, Gurindar S. Sohi:
Author retrospective for cooperative cache partitioning for chip multiprocessors. ICS 25th Anniversary 2014: 80-81 - [c76]Srinath Sridharan, Gagan Gupta, Gurindar S. Sohi:
Adaptive, efficient, parallel execution of parallel programs. PLDI 2014: 169-180 - [c75]Gagan Gupta, Srinath Sridharan, Gurindar S. Sohi:
Globally precise-restartable execution of parallel programs. PLDI 2014: 181-192 - 2013
- [c74]Srinath Sridharan, Gagan Gupta, Gurindar S. Sohi:
Holistic run-time parallelism management for time and energy efficiency. ICS 2013: 337-348 - 2012
- [j24]Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi:
Supporting Overcommitted Virtual Machines through Hardware Spin Detection. IEEE Trans. Parallel Distributed Syst. 23(2): 353-366 (2012) - [c73]Gagan Gupta, Srinath Sridharan, Gurindar S. Sohi:
Efficient, precise-restartable program execution on future multicores. Hot Chips Symposium 2012: 1-3 - 2011
- [c72]Gagan Gupta, Gurindar S. Sohi:
Dataflow execution of sequential imperative programs on multicore architectures. MICRO 2011: 59-70
2000 – 2009
- 2009
- [j23]Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Dynamic heterogeneity and the need for multicore virtualization. ACM SIGOPS Oper. Syst. Rev. 43(2): 5-14 (2009) - [c71]Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Mixed-mode multicore reliability. ASPLOS 2009: 169-180 - [c70]Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi:
Serialization sets: a dynamic dependence-based parallel execution model. PPoPP 2009: 85-96 - [p1]Gurindar S. Sohi, T. N. Vijaykumar:
Speculatively Multithreaded Architectures. Multicore Processors and Systems 2009: 111-143 - 2008
- [c69]Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Adapting to intermittent faults in multicore systems. ASPLOS 2008: 255-264 - [c68]Philip M. Wells, Gurindar S. Sohi:
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. HPCA 2008: 264-275 - 2007
- [c67]Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Adapting to Intermittent Faults in Future Multicore Systems. PACT 2007: 431 - [c66]Jichuan Chang, Gurindar S. Sohi:
Cooperative cache partitioning for chip multiprocessors. ICS 2007: 242-252 - 2006
- [c65]Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Hardware support for spin management in overcommitted virtual machines. PACT 2006: 124-133 - [c64]Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi:
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. ASPLOS 2006: 283-292 - [c63]Jichuan Chang, Gurindar S. Sohi:
Cooperative Caching for Chip Multiprocessors. ISCA 2006: 264-276 - [c62]Saisanthosh Balakrishnan, Gurindar S. Sohi:
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. ISCA 2006: 302-313 - 2004
- [j22]Allison L. Holloway, Gurindar S. Sohi:
Characterization of Problem Stores. IEEE Comput. Archit. Lett. 3 (2004) - [j21]Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi:
Speculative Incoherent Cache Protocols. IEEE Micro 24(6): 104-109 (2004) - [c61]Jaehyuk Huh, Jichuan Chang, Doug Burger, Gurindar S. Sohi:
Coherence decoupling: making use of incoherence. ASPLOS 2004: 97-106 - [c60]J. Adam Butts, Gurindar S. Sohi:
Use-Based Register Caching with Decoupled Indexing. ISCA 2004: 302-313 - [c59]Gurindar S. Sohi:
Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. MICRO 2004: 143 - 2003
- [c58]Paramjit S. Oberoi, Gurindar S. Sohi:
Parallelism in the Front-End. ISCA 2003: 230-240 - [c57]Saisanthosh Balakrishnan, Gurindar S. Sohi:
Exploiting Value Locality in Physical Register Files. MICRO 2003: 265-276 - 2002
- [j20]Andreas Moshovos, Gurindar S. Sohi:
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. IEEE Trans. Computers 51(3): 313-326 (2002) - [c56]J. Adam Butts, Gurindar S. Sohi:
Dynamic dead-instruction detection and elimination. ASPLOS 2002: 199-210 - [c55]Paramjit S. Oberoi, Gurindar S. Sohi:
Out-of-Order Instruction Fetch Using Multiple Sequencers. ICPP 2002: 14-26 - [c54]J. Adam Butts, Gurindar S. Sohi:
Characterizing and predicting value degree of use. MICRO 2002: 15-26 - [c53]Craig B. Zilles, Gurindar S. Sohi:
Master/slave speculative parallelization. MICRO 2002: 85-96 - [c52]Amir Roth, Gurindar S. Sohi:
A quantitative framework for automated pre-execution thread selection. MICRO 2002: 430-441 - 2001
- [j19]Gurindar S. Sohi, Amir Roth:
Speculative Multithreaded Processors. Computer 34(4): 66-71 (2001) - [j18]Amir Roth, Gurindar S. Sohi:
Squash Reuse via a Simplified Implementation of Register Integration. J. Instr. Level Parallelism 3 (2001) - [j17]Andreas Moshovos, Gurindar S. Sohi:
Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. Proc. IEEE 89(11): 1560-1575 (2001) - [j16]T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi:
Speculative Versioning Cache. IEEE Trans. Parallel Distributed Syst. 12(12): 1305-1317 (2001) - [c51]Gurindar S. Sohi:
Microprocessors - 10 Years Back, 10 Years Ahead. Informatics 2001: 209-218 - [c50]Amir Roth, Gurindar S. Sohi:
Speculative Data-Driven Multithreading. HPCA 2001: 37-48 - [c49]Craig B. Zilles, Gurindar S. Sohi:
A Programmable Co-Processor for Profiling. HPCA 2001: 241-252 - [c48]Craig B. Zilles, Gurindar S. Sohi:
Execution-based prediction using speculative slices. ISCA 2001: 2-13 - 2000
- [j15]Andreas Moshovos, Gurindar S. Sohi:
Memory Dependence Prediction in Multimedia Applications. J. Instr. Level Parallelism 2 (2000) - [c47]Gurindar S. Sohi:
Amir Roth: Speculative Multithreaded Processors. HiPC 2000: 259-270 - [c46]Andreas Moshovos, Gurindar S. Sohi:
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. HPCA 2000: 301-312 - [c45]Craig B. Zilles, Gurindar S. Sohi:
Understanding the backward slices of performance degrading instructions. ISCA 2000: 172-181 - [c44]J. Adam Butts, Gurindar S. Sohi:
A static power model for architects. MICRO 2000: 191-201 - [c43]Amir Roth, Gurindar S. Sohi:
Register integration: a simple and efficient implementation of squash reuse. MICRO 2000: 223-234
1990 – 1999
- 1999
- [j14]Andreas Moshovos, Gurindar S. Sohi:
Speculative Memory Cloaking and Bypassing. Int. J. Parallel Program. 27(6): 427-456 (1999) - [j13]T. N. Vijaykumar, Gurindar S. Sohi:
Task Selection for the Multiscalar Architecture. J. Parallel Distributed Comput. 58(2): 132-158 (1999) - [c42]Amir Roth, Andreas Moshovos, Gurindar S. Sohi:
Improving virtual function call target prediction via dependence-based pre-computation. International Conference on Supercomputing 1999: 356-364 - [c41]Amir Roth, Gurindar S. Sohi:
Effective Jump-Pointer Prefetching for Linked Data Structures. ISCA 1999: 111-121 - [c40]Andreas Moshovos, Gurindar S. Sohi:
Read-After-Read Memory Dependence Prediction. MICRO 1999: 177-185 - [c39]Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi:
The Use of Multithreading for Exception Handling. MICRO 1999: 219-229 - 1998
- [c38]Avinash Sodani, Gurindar S. Sohi:
An Empirical Analysis of Instruction Repetition. ASPLOS 1998: 35-45 - [c37]Amir Roth, Andreas Moshovos, Gurindar S. Sohi:
Dependance Based Prefetching for Linked Data Structures. ASPLOS 1998: 115-126 - [c36]Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi:
Speculative Versioning Cache. HPCA 1998: 195-205 - [c35]Gurindar S. Sohi:
Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 51-53 - [c34]Gurindar S. Sohi:
Retrospective: Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 111-114 - [c33]Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 329-336 - [c32]Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar:
Multiscalar Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 521-532 - [c31]T. N. Vijaykumar, Gurindar S. Sohi:
Task Selection for a Multiscalar Processor. MICRO 1998: 81-92 - [c30]Avinash Sodani, Gurindar S. Sohi:
Understanding the Differences Between Value Prediction and Instruction Reuse. MICRO 1998: 205-215 - [e2]Mateo Valero, Gurindar S. Sohi, Doug DeGroot:
Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998. IEEE Computer Society 1998, ISBN 0-8186-8491-7 [contents] - [e1]Gurindar S. Sohi:
25 Years of the International Symposia on Computer Architecture (Selected Papers). ACM 1998, ISBN 1-58113-058-9 [contents] - 1997
- [c29]Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
Dynamic Speculation and Synchronization of Data Dependences. ISCA 1997: 181-193 - [c28]Avinash Sodani, Gurindar S. Sohi:
Dynamic Instruction Reuse. ISCA 1997: 194-205 - [c27]Andreas Moshovos, Gurindar S. Sohi:
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. MICRO 1997: 235-245 - [r1]Doug Burger, James R. Goodman, Gurindar S. Sohi:
Memory Systems. The Computer Science and Engineering Handbook 1997: 447-461 - 1996
- [j12]Manoj Franklin, Gurindar S. Sohi:
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Trans. Computers 45(5): 552-571 (1996) - [c26]Todd M. Austin, Gurindar S. Sohi:
High-Bandwidth Address Translation for Multiple-Issue Processors. ISCA 1996: 158-167 - 1995
- [j11]James E. Smith, Gurindar S. Sohi:
The microarchitecture of superscalar processors. Proc. IEEE 83(12): 1609-1624 (1995) - [c25]Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi:
Streamlining Data Cache Access with Fast Address Calculation. ISCA 1995: 369-380 - [c24]Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar:
Multiscalar Processors. ISCA 1995: 414-425 - [c23]Todd M. Austin, Gurindar S. Sohi:
Zero-cycle loads: microarchitecture support for reducing load latency. MICRO 1995: 82-92 - 1994
- [j10]Alvin R. Lebeck, Gurindar S. Sohi:
Request Combining in Multiprocessors with Arbitrary Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 5(11): 1140-1155 (1994) - [c22]Dionisios N. Pnevmatikatos, Gurindar S. Sohi:
Guarded Executing and Branch Prediction in Dynamic ILP Processors. ISCA 1994: 120-129 - [c21]Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
The anatomy of the register file in a multiscalar processor. MICRO 1994: 181-190 - [c20]Todd M. Austin, Scott E. Breach, Gurindar S. Sohi:
Efficient Detection of All Pointer and Array Access Errors. PLDI 1994: 290-301 - 1993
- [j9]Gurindar S. Sohi:
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. IEEE Trans. Computers 42(1): 34-44 (1993) - [c19]Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi:
Control flow prediction for dynamic ILP processors. MICRO 1993: 153-163 - 1992
- [j8]MenChow Chiang, Gurindar S. Sohi:
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. IEEE Trans. Computers 41(3): 297-317 (1992) - [c18]Manoj Franklin, Gurindar S. Sohi:
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. ISCA 1992: 58-67 - [c17]Todd M. Austin, Gurindar S. Sohi:
Dynamic Dependency Analysis of Ordinary Programs. ISCA 1992: 342-351 - [c16]Manoj Franklin, Gurindar S. Sohi:
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. MICRO 1992: 236-245 - 1991
- [c15]Gurindar S. Sohi, Manoj Franklin:
High-Bandwidth Data Memory Systems for Superscalar Processors. ASPLOS 1991: 53-62 - [c14]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. ISCA 1991: 170-179 - [c13]MenChow Chiang, Gurindar S. Sohi:
Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. SIGMETRICS 1991: 90-100 - 1990
- [j7]Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain:
Scalable Shared-Memory Multiprocessor Architectures. Computer 23(6): 71-83 (1990) - [j6]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers 39(1): 63-71 (1990) - [j5]Gurindar S. Sohi:
Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. IEEE Trans. Computers 39(3): 349-359 (1990) - [j4]Gurindar S. Sohi, Wei-Chung Hsu:
The use of intermediate memories for low-latency memory access in supercomputer scalar units. J. Supercomput. 4(1): 5-21 (1990) - [j3]Steven L. Scott, Gurindar S. Sohi:
The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. IEEE Trans. Parallel Distributed Syst. 1(4): 385-398 (1990) - [c12]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
Exploitation of operation-level parallelism in a processor of the CRAY X-MP. ICCD 1990: 20-23
1980 – 1989
- 1989
- [j2]Mary K. Vernon, Rajeev Jog, Gurindar S. Sohi:
Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. Perform. Evaluation 9(4): 287-302 (1989) - [j1]Gurindar S. Sohi:
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. IEEE Trans. Computers 38(4): 484-492 (1989) - [c11]Gurindar S. Sohi, Sriram Vajapeyam:
Tradeoffs in Instruction Format Design for Horizontal Architectures. ASPLOS 1989: 15-25 - [c10]Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja:
A study of time-redundant fault tolerance techniques for high-performance pipelined computers. FTCS 1989: 436-443 - [c9]Gurindar S. Sohi, James E. Smith, James R. Goodman:
Restricted Fetch&Phi operations for parallel processing. ICS 1989: 410-416 - [c8]Steven L. Scott, Gurindar S. Sohi:
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. ISCA 1989: 167-176 - [c7]V. S. Madan, C.-J. Peng, Gurindar S. Sohi:
On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. NACLP 1989: 888-906 - 1988
- [c6]Andrew R. Pleszkun, Gurindar S. Sohi:
The Performance Potential of Multiple Functional Unit Processors. ISCA 1988: 37-44 - [c5]Andrew R. Pleszkun, Gurindar S. Sohi:
Multiple instruction issue and single-chip processors. MICRO 1988: 64-66 - 1987
- [c4]Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. ISCA 1987: 27-34 - [c3]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. ISCA 1987: 224-231 - 1986
- [c2]Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson:
Features of the Structured Memory Access (SMA) Architecture. COMPCON 1986: 259-265 - 1985
- [b1]Gurindar S. Sohi:
Blast: A Machine Architecture for High-Speed List Processing Using Associative Tables (Traversal, Pointers). University of Illinois Urbana-Champaign, USA, 1985 - [c1]Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel:
An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA 1985: 91-98
Coauthor Index
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