default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID24th ISCA 1997: Denver, Colorado, USA
- Andrew R. Pleszkun, Trevor N. Mudge:
Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997. ACM 1997, ISBN 0-89791-901-7
Caching Techniques for Instruction Level Parallelism
- Sriram Vajapeyam, Tulika Mitra:
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. 1-12 - Ravi Nair, Martin E. Hopkins:
Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups. 13-25 - Kemal Ebcioglu, Erik R. Altman:
DAISY: Dynamic Compilation for 100% Architectural Compatibility. 26-37
Networks and Input/Output
- Timothy Mark Pinkston, Sugath Warnakulasuriya:
On Deadlocks in Interconnection Networks. 38-49 - Craig B. Stunkel, Rajeev Sivaram, Dhabaleswar K. Panda:
Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their Impact. 50-61 - Guillermo A. Alvarez, Walter A. Burkhard, Flaviu Cristian:
Tolerating Multiple Failures in RAID Architectures with Optimal Storage and Uniform Declustering. 62-72
Multiprocessors
- Dan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz:
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors. 73-84 - Richard P. Martin, Amin Vahdat, David E. Culler, Thomas E. Anderson:
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture. 85-97 - Wolf-Dietrich Weber, Stephen Gold, Pat Helland, Takeshi Shimizu, Thomas Wicki, Winfried W. Wilcke:
The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance Servers. 98-107
Memory System Design
- Ziyad S. Hakura, Anoop Gupta:
The Design and Analysis of a Cache Architecture for Texture Mapping. 108-120 - Kenneth M. Wilson, Kunle Olukotun:
Designing High Bandwidth On-Chip Caches. 121-132 - Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
Memory-System Design Considerations for Dynamically-Scheduled Processors. 133-143
Issues in Shared Memory Systems
- Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, Sarita V. Adve:
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems. 144-156 - Leonidas I. Kontothanassis, Galen C. Hunt, Robert Stets, Nikos Hardavellas
, Michal Cierniak, Srinivasan Parthasarathy, Wagner Meira Jr., Sandhya Dwarkadas, Michael L. Scott:
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks. 157-169 - Alain Kägi, Doug Burger, James R. Goodman:
Efficient Synchronization: Let Them Eat QOLB. 170-180
Improving Instruction Level Parallelism
- Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
Dynamic Speculation and Synchronization of Data Dependences. 181-193 - Avinash Sodani, Gurindar S. Sohi:
Dynamic Instruction Reuse. 194-205 - Subbarao Palacharla, Norman P. Jouppi, James E. Smith:
Complexity-Effective Superscalar Processors. 206-218
NUMA and COMA Architectures
- Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott:
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. 219-228 - Babak Falsafi, David A. Wood:
Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA. 229-240 - James Laudon, Daniel Lenoski:
The SGI Origin: A ccNUMA Highly Scalable Server. 241-251
Prefetching and Prediction
- Doug Joseph, Dirk Grunwald:
Prefetching Using Markov Predictors. 252-263 - Vatsa Santhanam, Edward H. Gornish, Wei-Chung Hsu:
Data Prefetching on the HP PA-8000. 264-273 - Po-Yung Chang, Eric Hao, Yale N. Patt:
Target Prediction for Indirect Jumps. 274-283
Branch Prediction
- Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt:
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. 284-291 - Pierre Michaud, André Seznec, Richard Uhlig:
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. 292-303 - Joel S. Emer, Nicholas C. Gloy:
A Language for Describing Predictors and Its Application to Automatic Synthesis. 304-314
Managing the Memory Hierarchy and Memory-Centric Architectures
- Teresa L. Johnson, Wen-mei W. Hwu:
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis. 315-326 - Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson, Thomas E. Anderson, Katherine A. Yelick:
The Energy Efficiency of IRAM Architectures. 327-337 - Doug Burger, Stefanos Kaxiras, James R. Goodman:
DataScalar Architectures. 338-349
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
