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2020 – today
- 2023
[c80]Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu:
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD 2023: 614-622- [c79]Chia-Jo Lin, Shih-Hsu Huang, Wan-Yi Hsueh, Wei-Chung Hsu, Chih-Wen Su:
An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea. ICCE-Taiwan 2023: 309-310 - 2022
- [j29]Horng-Ruey Huang
, Ding-Yong Hong, Jan-Jan Wu, Kung-Fu Chen, Pangfeng Liu, Wei-Chung Hsu:
Accelerating Video Captioning on Heterogeneous System Architectures. ACM Trans. Archit. Code Optim. 19(3): 38:1-38:25 (2022) - [c78]Yi You, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu, Wei-Chung Hsu:
Accelerating Convolutional Neural Networks via Inter-operator Scheduling. ICPADS 2022: 916-923 - 2021
- [c77]Pin-Wei Liao, Wei-Chung Hsu, Shih-Wei Liao:
Intra- and Inter- Layer Transformation to Reduce Memory Traffic for CNN Computation. ICPP Workshops 2021: 14:1-14:5 - [c76]Horng-Ruey Huang, Ding-Yong Hong, Jan-Jan Wu, Pangfeng Liu, Wei-Chung Hsu:
Efficient Video Captioning on Heterogeneous System Architectures. IPDPS 2021: 1035-1045
2010 – 2019
- 2019
- [j28]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator. J. Syst. Archit. 98: 173-190 (2019) - [j27]Ding-Yong Hong, Jan-Jan Wu, Yu-Ping Liu, Sheng-Yu Fu, Wei-Chung Hsu:
Processor-Tracing Guided Region Formation in Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 15(4): 52:1-52:25 (2019) - [j26]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 16(1): 2:1-2:24 (2019) - [c75]Sheng-Yu Fu, Wei-Chung Hsu:
Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures. CGO 2019: 275 - [c74]Chih-Min Lin, Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Vector Processing in Dynamic Binary Translation. ICPP 2019: 93:1-93:10 - [c73]Zi Xuan Huang, Sheng-Yu Fu, Wei-Chung Hsu:
Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous Systems. SAMOS 2019: 51-64 - 2018
- [j25]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Efficient and retargetable SIMD translation in a dynamic binary translator. Softw. Pract. Exp. 48(6): 1312-1330 (2018) - [j24]Ding-Yong Hong, Yu-Ping Liu, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD Parallelism via Dynamic Binary Translation. ACM Trans. Embed. Comput. Syst. 17(3): 61:1-61:27 (2018) - [j23]Chih-Chen Kao, Wei-Chung Hsu:
Exploring hidden coherency of Ray-Tracing for heterogeneous systems using online feedback methodology. Vis. Comput. 34(5): 633-643 (2018) - [c72]Sheng-Yu Fu, Chih-Min Lin, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator. CASES 2018: 14:1-14:3 - [c71]Chih-Yung Liang, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu:
Automatically Migrating Sequential Applications to Heterogeneous System Architecture. HPCS 2018: 114-121 - [c70]Shih-Kai Lin, Ding-Yong Hong, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic tuning of applications using restricted transactional memory. RACS 2018: 249-254 - [c69]Liang-Chi Tseng, Wei-Chung Hsu:
Efficient synthetic light field generation using adaptive multi-level rendering. RACS 2018: 313-318 - 2017
- [j22]Jiunn-Yeu Chen, Wuu Yang, Wei-Chung Hsu, Bor-Yeh Shen, Quan-Huei Ou:
On Static Binary Translation of ARM/Thumb Mixed ISA Binaries. ACM Trans. Embed. Comput. Syst. 16(3): 81:1-81:25 (2017) - [j21]Chih-Chen Kao, Yu-Tsung Miao, Wei-Chung Hsu:
A Pipeline-Based Ray-Tracing Runtime System for HSA-Compliant Frameworks. IEEE Trans. Multim. 19(11): 2450-2462 (2017) - [c68]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation. PACT 2017: 343-355 - [c67]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions. LCTES 2017: 31-40 - [c66]Chih-Chen Kao, Liang-Chi Tseng, Wei-Chung Hsu:
Efficient Synthetic Light Field Rendering on Heterogeneous Systems Using a Pipeline-Based Runtime Design. RACS 2017: 94-99 - [c65]Kuo-You Peng, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu:
Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systems. SAMOS 2017: 105-112 - [c64]Zhe Wang, Chenggang Wu, Jianjun Li, Yuanming Lai, Xiangyu Zhang, Wei-Chung Hsu, Yueqiang Cheng:
ReRanz: A Light-Weight Virtual Machine to Mitigate Memory Disclosure Attacks. VEE 2017: 143-156 - 2016
- [j20]Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu:
Optimizing Control Transfer and Memory Virtualization in Full System Emulators. ACM Trans. Archit. Code Optim. 12(4): 47:1-47:24 (2016) - [c63]Chih-Chen Kao, Yu-Tsung Miao, Wei-Chung Hsu:
A pipeline-based runtime technique for improving Ray-Tracing on HSA-compliant systems. ICME 2016: 1-6 - [c62]Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Longer SIMD Lanes in Dynamic Binary Translation. ICPADS 2016: 853-860 - [c61]Hao-Che Hsu, Chih Wei Yeh, Shih-Hao Hung, Wei-Chung Hsu, Chung-Ta King, Yeh-Ching Chung:
HSAemu 2.0: Full System Emulation for HSA platforms with Soft-MMU. RACS 2016: 230-235 - [c60]Yu-Ju Huang, Hsuan-Heng Wu, Yeh-Ching Chung, Wei-Chung Hsu:
Building a KVM-based Hypervisor for a Heterogeneous System Architecture Compliant System. VEE 2016: 3-15 - 2015
- [j19]Jiunn-Yeu Chen, Wuu Yang, Bor-Yeh Shen, Yuan-Jia Li, Wei-Chung Hsu:
Automatic validation for binary translation. Comput. Lang. Syst. Struct. 43: 96-115 (2015) - [j18]Chun-Chen Hsu, Ding-Yong Hong, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu:
A dynamic binary translation system in a client/server environment. J. Syst. Archit. 61(7): 307-319 (2015) - [j17]Chih-Chen Kao, Wei-Chung Hsu:
An Adaptive Heterogeneous Runtime Framework for Irregular Applications. J. Signal Process. Syst. 80(3): 245-259 (2015) - [c59]Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD code generation in QEMU. DATE 2015: 1233-1236 - [c58]Chih-Chen Kao, Wei-Chung Hsu:
Runtime techniques for efficient Ray-Tracing on heterogeneous systems. DSP 2015: 100-104 - [c57]Sheng-Yu Fu, Ding-Yong Hong, Jan-Jan Wu, Pangfeng Liu, Wei-Chung Hsu:
SIMD Code Translation in an Enhanced HQEMU. ICPADS 2015: 507-514 - [c56]Zhe Wang, Jianjun Li, Chenggang Wu, Dongyan Yang, Zhenjiang Wang, Wei-Chung Hsu, Bin Li, Yong Guan:
HSPT: Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA System Virtual Machines. VEE 2015: 53-64 - 2014
- [j16]Bor-Yeh Shen, Wei-Chung Hsu, Wuu Yang:
A Retargetable Static Binary Translator for the ARM Architecture. ACM Trans. Archit. Code Optim. 11(2): 18:1-18:25 (2014) - [j15]I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung:
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13(4): 92:1-92:28 (2014) - [j14]Ding-Yong Hong, Jan-Jan Wu, Pen-Chung Yew, Wei-Chung Hsu, Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Yeh-Ching Chung:
Efficient and Retargetable Dynamic Binary Translation on Multicores. IEEE Trans. Parallel Distributed Syst. 25(3): 622-632 (2014) - [c55]Jianjun Li, Zhenjiang Wang, Chenggang Wu, Wei-Chung Hsu, Di Xu:
Dynamic and Adaptive Calling Context Encoding. CGO 2014: 120 - [c54]Jiun-Hung Ding, Wei-Chung Hsu, BaiCheng Jeng, Shih-Hao Hung, Yeh-Ching Chung:
HSAemu - A full system emulator for HSA platforms. CODES+ISSS 2014: 26:1-26:10 - [c53]James R. Goodman, Wei-Chung Hsu:
Author retrospective for code scheduling and register allocation in large basic blocks. ICS 25th Anniversary 2014: 4-5 - [c52]Chih-Chen Kao, Wei-Chung Hsu:
An Adaptive Heterogeneous Runtime for Irregular Applications in the Case of Ray-Tracing (Extended Abstract). NPC 2014: 604-607 - [c51]Chao-Rui Chang, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Pen-Chung Yew:
Efficient memory virtualization for Cross-ISA system mode emulation. VEE 2014: 117-128 - [c50]Yi-Hong Lyu, Ding-Yong Hong, Tai-Yi Wu, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Pen-Chung Yew:
DBILL: an efficient and retargetable dynamic binary instrumentation framework using llvm backend. VEE 2014: 141-152 - 2013
- [j13]Yangchun Luo, Wei-Chung Hsu, Antonia Zhai:
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution. ACM Trans. Archit. Code Optim. 10(4): 26:1-26:29 (2013) - [c49]Jiunn-Yeu Chen, Bor-Yeh Shen, Quan-Huei Ou, Wuu Yang, Wei-Chung Hsu:
Effective code discovery for ARM/Thumb mixed ISA binaries in a static binary translator. CASES 2013: 19:1-19:10 - [c48]Chun-Chen Hsu, Pangfeng Liu, Jan-Jan Wu, Pen-Chung Yew, Ding-Yong Hong, Wei-Chung Hsu, Chien-Min Wang:
Improving dynamic binary optimization through early-exit guided code region formation. VEE 2013: 23-32 - 2012
- [j12]Hsiung-Cheng Lin, Chao-Hung Chen, Guo-Shing Huang, Ying-Chu Liu, Wei-Chung Hsu:
Design of communication interface and control system for intelligent humanoid robot. Comput. Appl. Eng. Educ. 20(3): 454-467 (2012) - [j11]Ragavendra Natarajan, Vineeth Mekkat, Wei-Chung Hsu, Antonia Zhai:
Effectiveness of Compiler-Directed Prefetching on Data Mining Benchmarks. J. Circuits Syst. Comput. 21(2) (2012) - [c47]Guillermo A. Pérez, Chung-Min Kao, Yeh-Ching Chung, Wei-Chung Hsu:
A hybrid just-in-time compiler for android: comparing JIT types and the result of cooperation. CASES 2012: 41-50 - [c46]Bor-Yeh Shen, Jiunn-Yeu Chen, Wei-Chung Hsu, Wuu Yang:
LLBT: an LLVM-based static binary translator. CASES 2012: 51-60 - [c45]Ding-Yong Hong, Chun-Chen Hsu, Pen-Chung Yew, Jan-Jan Wu, Wei-Chung Hsu, Pangfeng Liu, Chien-Min Wang, Yeh-Ching Chung:
HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores. CGO 2012: 104-113 - [c44]Bor-Yeh Shen, Jyun-Yan You, Wuu Yang, Wei-Chung Hsu:
An LLVM-based hybrid binary translation system. SIES 2012: 229-236 - 2011
- [j10]Jianjun Li, Chenggang Wu, Wei-Chung Hsu:
Efficient and effective misaligned data access handling in a dynamic binary translation system. ACM Trans. Archit. Code Optim. 8(2): 7:1-7:29 (2011) - [c43]Chih-Sheng Wang, Guillermo A. Pérez, Yeh-Ching Chung, Wei-Chung Hsu, Wei-Kuan Shih, Hong-Rong Hsu:
A method-based ahead-of-time compiler for android applications. CASES 2011: 15-24 - [c42]Jianjun Li, Chenggang Wu, Wei-Chung Hsu:
Dynamic register promotion of stack variables. CGO 2011: 21-31 - [c41]Jiun-Hung Ding, Po-Chun Chang, Wei-Chung Hsu, Yeh-Ching Chung:
PQEMU: A Parallel System Emulator Based on QEMU. ICPADS 2011: 276-283 - [c40]Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Jan-Jan Wu, Ding-Yong Hong, Pen-Chung Yew, Wei-Chung Hsu:
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends. ICPP 2011: 226-234 - 2010
- [j9]Chao-Hung Chen, Hsiung-Cheng Lin, Ying-Chu Liu, Wei-Chung Hsu:
Local-loop based robot action control module using independent microprocessors. Comput. Appl. Eng. Educ. 18(4): 593-606 (2010) - [c39]Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai:
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems. PACT 2010: 453-464
2000 – 2009
- 2009
- [c38]Jianjun Li, Chenggang Wu, Wei-Chung Hsu:
An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems. CGO 2009: 180-189 - [c37]Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu:
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. CSE (2) 2009: 174-181 - [c36]Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas:
Dynamic performance tuning for speculative threads. ISCA 2009: 462-473 - [c35]Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew, Tin-Fook Ngai:
Exploring speculative parallelism in SPEC2006. ISPASS 2009: 77-88 - 2008
- [c34]Chao-Hung Chen, Hsiung-Cheng Lin, Ying-Chu Liu, Wei-Chung Hsu, Shin-Ming Chang:
Sufficient sunlight supply for home care using local closed-loop shutter control system. SMC 2008: 2270-2275 - [i1]Erik R. Altman, Bruce R. Childers, Robert S. Cohn, Jack W. Davidson, Koen De Bosschere, Bjorn De Sutter, M. Anton Ertl, Michael Franz, Yuan Xiang Gu, Matthias Hauswirth, Thomas Heinz, Wei-Chung Hsu, Jens Knoop, Andreas Krall, Naveen Kumar, Jonas Maebe, Robert Muth, Xavier Rival, Erven Rohou, Roni Rosner, Mary Lou Soffa, Jens Tröger, Christopher A. Vick:
08441 Final Report - Emerging Uses and Paradigms for Dynamic Binary Translation. Emerging Uses and Paradigms for Dynamic Binary Translation 2008 - 2007
- [j8]Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas M. Hawkins, Wei-Chung Hsu, Pen-Chung Yew:
CIM: A Reliable Metric for Evaluating Program Phase Classifications. IEEE Comput. Archit. Lett. 6(1): 9-12 (2007) - [c33]Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew, Sreekumar R. Nair, Robert Y. Geva:
Entropy-Based Profile Characterization and Classification for Automatic Profile Management. Asia-Pacific Computer Systems Architecture Conference 2007: 40-51 - [c32]Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew:
COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications. ICPP 2007: 25 - [c31]Wen-Chuan Hsieh, Wei-Chung Hsu, Yu-Yuan Hsu:
An Architecture for the Interoperability of Multimedia Messaging Services between GPRS and PHS Cellular Networks. IIH-MSP 2007: 365-368 - [c30]Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew:
Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization. IISWC 2007: 139-148 - 2006
- [j7]Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
Recovery code generation for general speculative optimizations. ACM Trans. Archit. Code Optim. 3(1): 67-89 (2006) - [c29]Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu:
A Study of the Performance Potential for Dynamic Instruction Hints Selection. Asia-Pacific Computer Systems Architecture Conference 2006: 67-80 - [c28]Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu:
Issues and Support for Dynamic Register Allocation. Asia-Pacific Computer Systems Architecture Conference 2006: 351-358 - [c27]Abhinav Das, Jiwei Lu, Wei-Chung Hsu:
Region Monitoring for Local Phase Detection in Dynamic Optimization Systems. CGO 2006: 124-134 - [c26]Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew:
Supporting Speculative Multithreading on Simultaneous Multithreaded Processors. HiPC 2006: 148-158 - 2005
- [c25]Abhinav Das, Jiwei Lu, Howard Chen, Jinpyo Kim, Pen-Chung Yew, Wei-Chung Hsu, Dong-yuan Chen:
Performance of Runtime Optimization on BLAST. CGO 2005: 86-96 - [c24]Xiaoru Dai, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew:
A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion. CGO 2005: 280-290 - [c23]Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, David J. Lilja, Pen-Chung Yew:
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations. HiPEAC 2005: 203-217 - [c22]Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham:
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor. MICRO 2005: 93-104 - 2004
- [j6]Jiwei Lu, Howard Chen, Pen-Chung Yew, Wei-Chung Hsu:
Design and Implementation of a Lightweight Dynamic Optimization System. J. Instr. Level Parallelism 6 (2004) - [j5]Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
A compiler framework for speculative optimizations. ACM Trans. Archit. Code Optim. 1(3): 247-271 (2004) - [c21]Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. IEEE PACT 2004: 17-28 - [c20]Howard Chen, Jiwei Lu, Wei-Chung Hsu, Pen-Chung Yew:
Continuous Adaptive Object-Code Re-optimization Framework. Asia-Pacific Computer Systems Architecture Conference 2004: 241-255 - [c19]Tong Chen, Jin Lin, Xiaoru Dai, Wei-Chung Hsu, Pen-Chung Yew:
Data Dependence Profiling for Speculative Optimizations. CC 2004: 57-72 - 2003
- [c18]Howard Chen, Wei-Chung Hsu, Dong-yuan Chen:
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling. CGO 2003: 79-90 - [c17]Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew:
Speculative Register Promotion Using Advanced Load Address Table (ALAT). CGO 2003: 125-134 - [c16]Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen:
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. MICRO 2003: 180-190 - [c15]Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
A compiler framework for speculative analysis and optimizations. PLDI 2003: 289-299 - 2002
- [c14]Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yuan Chen:
On the Predictability of Program Behavior Using Different Input Data Sets. Interaction between Compilers and Computer Architectures 2002: 45-53 - [c13]Tong Chen, Jin Lin, Wei-Chung Hsu, Pen-Chung Yew:
On the Impact of Naming Methods for Heap-Oriented Pointers in C Programs. ISPAN 2002: 251- - [c12]Tong Chen, Jin Lin, Wei-Chung Hsu, Pen-Chung Yew:
An Empirical Study on the Granularity of Pointer Analysis in C Programs. LCPC 2002: 157-171
1990 – 1999
- 1998
- [j4]Wei-Chung Hsu, James E. Smith:
A Performance Study of Instruction Cache Prefetching Methods. IEEE Trans. Computers 47(5): 497-508 (1998) - 1997
- [c11]Vatsa Santhanam, Edward H. Gornish, Wei-Chung Hsu:
Data Prefetching on the HP PA-8000. ISCA 1997: 264-273 - 1996
- [c10]David A. Dunn, Wei-Chung Hsu:
Instruction Scheduling for the HP PA-8000. MICRO 1996: 298-307 - 1993
- [j3]Sriram Vajapeyam, Wei-Chung Hsu:
Toward Effective Scalar Hardware for Highly Vectorizable Applications. J. Parallel Distributed Comput. 19(3): 147-162 (1993) - [c9]Wei-Chung Hsu, James E. Smith:
Performance of Cached DRAM Organizations in Vector Supercomputers. ISCA 1993: 327-336 - 1992
- [c8]Sriram Vajapeyam, Wei-Chung Hsu:
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. MICRO 1992: 20-28 - [c7]James E. Smith, Wei-Chung Hsu:
Prefetching in Supercomputer Instruction Caches. SC 1992: 588-597 - 1991
- [c6]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. ISCA 1991: 170-179 - 1990
- [j2]Gurindar S. Sohi, Wei-Chung Hsu:
The use of intermediate memories for low-latency memory access in supercomputer scalar units. J. Supercomput. 4(1): 5-21 (1990) - [c5]Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu:
Exploitation of operation-level parallelism in a processor of the CRAY X-MP. ICCD 1990: 20-23 - [c4]James E. Smith, Wei-Chung Hsu, Christopher C. Hsiung:
Future general purpose supercomputer architectures. SC 1990: 796-804
1980 – 1989
- 1989
- [j1]Wei-Chung Hsu, Charles N. Fischer, James R. Goodman:
On the Minimization of Loads/Stores in Local Register Allocation. IEEE Trans. Software Eng. 15(10): 1252-1260 (1989) - 1988
- [c3]James R. Goodman, Wei-Chung Hsu:
Code scheduling and register allocation in large basic blocks. ICS 1988: 442-452 - 1987
- [c2]Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter:
WISQ: A Restartable Architecture Using Queues. ISCA 1987: 290-299 - 1986
- [c1]James R. Goodman, Wei-Chung Hsu:
On the Use of Registers vs. Cache to Minimize Memory Traffic. ISCA 1986: 375-383
Coauthor Index
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