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2020 – today
- 2024
[c61]Jiun-Kai Yang, Yao-Hua Chen, Chih-Tsun Huang:
BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive Distillation. SOCC 2024: 1-6- 2023
- [c60]Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu:
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD 2023: 614-622 - [c59]Chih-Tsun Huang
, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang:
Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD 2023: 187-193 - [c58]Jie-Ying Li, Herman Prawiro, Chia-Chen Chiang, Hsin-Yu Chang, Tse-Yu Pan, Chih-Tsun Huang, Min-Chun Hu:
Efficient Hand Gesture Recognition using Multi-Task Multi-Modal Learning and Self-Distillation. MMAsia 2023: 39:1-39:7 - [c57]Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou:
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC 2023: 1-6 - 2022
- [c56]Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou:
Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control. AICAS 2022: 506 - [c55]Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT 2022: 1-4 - 2021
- [c54]Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-Yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu:
Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS 2021: 1-4 - [c53]Che-Hao Chang, Chih-Tsun Huang:
Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator. SoCC 2021: 152-157
2010 – 2019
- 2019
- [c52]Hao-Ning Wu, Chih-Tsun Huang:
Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators. DATE 2019: 120-125 - [c51]Yueh-Chi Wu, Chih-Tsun Huang:
Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices. VLSI-DAT 2019: 1-4 - 2017
- [c50]Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT 2017: 1-4 - [c49]Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu:
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT 2017: 1-4 - 2016
- [c48]Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes:
IoT: Source of test challenges. ETS 2016: 1-10 - 2015
- [c47]Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou:
Design of a scalable many-core processor for embedded applications. ASP-DAC 2015: 24-25 - [c46]Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien:
Application-level embedded communication tracer for many-core systems. ASP-DAC 2015: 803-808 - 2014
- [c45]Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291 - [c44]Hsin-Yu Ting, Chih-Tsun Huang:
Design of low-cost elliptic curve cryptographic engines for ubiquitous security. VLSI-DAT 2014: 1-4 - 2013
- [j11]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [c43]Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou:
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. MES 2013: 41-44 - 2012
- [c42]Jyu-Yuan Lai, Po-Yu Chen, Ting-Shuo Hsu, Chih-Tsun Huang, Jing-Jia Liou:
Design and analysis of a many-core processor architecture for multimedia applications. APSIPA 2012: 1-6 - 2011
- [j10]Jyu-Yuan Lai, Chih-Tsun Huang:
Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1512-1517 (2011) - [c41]Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung:
TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. ASP-DAC 2011: 97-98 - [c40]Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang:
Reliability analysis and improvement for multi-level non-volatile memories with soft information. DAC 2011: 753-758 - [c39]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - [c38]Shuo-Hung Chen, Hsiao-Mei Lin, Hsin-Wen Wei, Yi-Cheng Chen, Chih-Tsun Huang, Yeh-Ching Chung:
Hardware/software co-designed accelerator for vector graphics applications. SASP 2011: 108-114 - 2010
- [j9]Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang:
Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 541-552 (2010) - [c37]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348 - [c36]Jyu-Yuan Lai, Tzu-Yu Hung, Kai-Hsiang Yang, Chih-Tsun Huang:
High-performance architecture for Elliptic Curve Cryptography over binary field. ISCAS 2010: 3933-3936
2000 – 2009
- 2009
- [j8]Jyu-Yuan Lai, Chih-Tsun Huang:
A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 394-398 (2009) - 2008
- [j7]Jyu-Yuan Lai, Chih-Tsun Huang:
Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1567-1580 (2008) - [c35]Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS 2008: 245-250 - [c34]Ming-Chang Hsieh, Chih-Tsun Huang:
An embedded infrastructure of debug and trace interface for the DSP platform. DAC 2008: 866-871 - 2007
- [j6]Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang:
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. 1(6): 716-723 (2007) - [j5]Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1303-1310 (2007) - [c33]Shin-Yi Lin, Chih-Tsun Huang:
A High-Throughput Low-Power AES Cipher for Network Applications. ASP-DAC 2007: 595-600 - [c32]Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang:
A prototype of a wireless-based test system. SoCC 2007: 225-228 - 2006
- [c31]Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495 - [c30]Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang:
Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17 - 2005
- [c29]Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu:
A configurable AES processor for enhanced security. ASP-DAC 2005: 361-366 - [c28]Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Design and test of a scalable security processor. ASP-DAC 2005: 372-375 - [c27]Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen:
A systematic approach to reducing semiconductor memory test time in mass production. MTDT 2005: 97-102 - [c26]Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu:
A BIST Scheme for FPGA Interconnect Delay Faults. VTS 2005: 201-206 - 2004
- [c25]Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC 2004: 456-458 - [c24]Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu:
On Test and Diagnostics of Flash Memories. Asian Test Symposium 2004: 260-265 - [c23]Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu:
Failure Factor Based Yield Enhancement for SRAM Designs. DFT 2004: 20-28 - [c22]Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT 2004: 478-486 - [c21]Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222 - 2003
- [j4]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A high-throughput low-cost AES processor. IEEE Commun. Mag. 41(12): 86-91 (2003) - [j3]Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu:
Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. 52(4): 386-399 (2003) - [c20]Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
Design of a scalable RSA and ECC crypto-processor. ASP-DAC 2003: 495-498 - [c19]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A highly efficient AES cipher chip. ASP-DAC 2003: 561-562 - [c18]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c17]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38 - [c16]Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253 - 2002
- [j2]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 480-490 (2002) - [c15]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c14]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - [c13]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141 - [c12]Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC 2002: 37-46 - [c11]Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288 - 2001
- [c10]Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96 - [c9]Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- - [c8]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306 - [c7]Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767 - 2000
- [c6]Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu:
A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12 - [c5]Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai:
BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299- - [c4]Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471 - [c3]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS 2000: 291-296
1990 – 1999
- 1999
- [j1]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang:
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16(1): 59-70 (1999) - [c2]Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES: A Fast Memory Fault Simulator. DFT 1999: 165-173 - 1997
- [c1]Chih-Tsun Huang, Cheng-Wen Wu:
High-speed C-testable systolic array design for Galois-field inversion. ED&TC 1997: 342-346
Coauthor Index
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