"A systematic approach to reducing semiconductor memory test time in mass ..."

Jen-Chieh Yeh et al. (2005)

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DOI: 10.1109/MTDT.2005.15

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - https://dblp.org/rec/conf/mtdt/YehKWHC05
Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen:
A systematic approach to reducing semiconductor memory test time in mass production. MTDT 2005: 97-102

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