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2020 – today
- 2023
[c58]Chun-Yeh Wang, Chien-Hsing Liang, Jing-Jia Liou, Harry H. Chen:
Signal Reduction of Signature Blocks for Transient Fault Debugging. ATS 2023: 1-6- [c57]Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu:
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD 2023: 614-622 - [c56]Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou:
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC 2023: 1-6 - 2022
- [c55]Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou:
Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control. AICAS 2022: 506 - [c54]Zih-Ming Huang, Dun-An Yang, Jing-Jia Liou, Harry H. Chen:
FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. ATS 2022: 144-149 - [c53]Jin-Fu Li, Jing-Jia Liou:
Foreword: ATS 2022. ATS 2022: x - [c52]Dun-An Yang, Jing-Jia Liou, Harry H. Chen:
Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging. ITC 2022: 73-81 - [c51]Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT 2022: 1-4 - 2021
- [c50]Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-Yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu:
Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS 2021: 1-4 - [c49]Dun-An Yang, Jing-Jia Liou, Harry H. Chen:
Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. ATS 2021: 133-138 - [c48]Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen:
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. ITC 2021: 10-19 - 2020
- [c47]Jiang-Tang Xiao, Ting-Shuo Hsu, Christian M. Fuchs, Yu-Teng Chang, Jing-Jia Liou, Harry H. Chen:
An ISA-level Accurate Fault Simulator for System-level Fault Analysis. ATS 2020: 1-6
2010 – 2019
- 2019
- [c46]Chia-Wei Chang, Zi-Qi Zhong, Jing-Jia Liou:
A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis. FPGA 2019: 309 - [c45]Yi-Che Lee, Ting-Shuo Hsu, Chun-Tse Chen, Jing-Jia Liou, Juin-Ming Lu:
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. VLSI-DAT 2019: 1-4 - 2017
- [c44]Zih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
Post-Silicon Test Flow for Aging Prediction. ATS 2017: 70-75 - [c43]Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT 2017: 1-4 - [c42]Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu:
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT 2017: 1-4 - 2015
- [j9]Tsun-Hsien Wang, Cheng-Wen Chiu, Wei-Chen Wu, Jen-Wen Wang, Chun-Yi Lin, Ching-Te Chiu, Jing-Jia Liou:
Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. IEEE Trans. Multim. 17(4): 470-484 (2015) - [c41]Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou:
Design of a scalable many-core processor for embedded applications. ASP-DAC 2015: 24-25 - [c40]Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, Jing-Jia Liou:
A fast and accurate network-on-chip timing simulator with a flit propagation model. ASP-DAC 2015: 797-802 - [c39]Jing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen:
Cost reduction of system-level tests with stressed structural tests and SVM. VLSI-SoC 2015: 177-182 - 2014
- [c38]Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Chip clustering with mutual information on multiple clock tests and its application to yield tuning. ICCD 2014: 243-248 - [c37]Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291 - 2013
- [j8]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [c36]Shuo-You Hsu, Chih-Hsiang Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
A Region-Based Framework for Design Feature Identification of Systematic Process Variations. Asian Test Symposium 2013: 265-270 - [c35]Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou:
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. MES 2013: 41-44 - 2012
- [c34]Jyu-Yuan Lai, Po-Yu Chen, Ting-Shuo Hsu, Chih-Tsun Huang, Jing-Jia Liou:
Design and analysis of a many-core processor architecture for multimedia applications. APSIPA 2012: 1-6 - [c33]Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou:
On error modeling of electrical bugs for post-silicon timing validation. ASP-DAC 2012: 701-706 - [c32]Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data. Asian Test Symposium 2012: 320-325 - 2011
- [j7]Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin:
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20(8): 1547-1569 (2011) - [c31]Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung:
TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. ASP-DAC 2011: 97-98 - [c30]Jing-Jia Liou, Ying-Yen Chen, Chun-Chia Chen, Chung-Yen Chien, Kuo-Li Wu:
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs. ASP-DAC 2011: 279-284 - [c29]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - 2010
- [j6]Chun-Yu Yang, Ying-Yen Chen, Sung-Yu Chen, Jing-Jia Liou:
Automatic Test Wrapper Synthesis for a Wireless ATE Platform. IEEE Des. Test Comput. 27(3): 31-41 (2010) - [c28]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348
2000 – 2009
- 2009
- [c27]Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, Jing-Jia Liou:
Multiple-Core under Test Architecture for HOY Wireless Testing Platform. Asian Test Symposium 2009: 275-280 - [c26]Ying-Yen Chen, Jing-Jia Liou:
A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. Asian Test Symposium 2009: 343-348 - 2008
- [j5]Ying-Yen Chen, Jing-Jia Liou:
Diagnosis Framework for Locating Failed Segments of Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 755-765 (2008) - [c25]Ming-Ting Hsieh, Shun-Yen Lu, Jing-Jia Liou, Augusli Kifli:
High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths. ATS 2008: 131-136 - [c24]Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS 2008: 245-250 - 2007
- [j4]Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang:
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Comput. Digit. Tech. 1(6): 716-723 (2007) - [c23]Ying-Yen Chen, Jing-Jia Liou:
Extraction of Statistical Timing Profiles Using Test Data. DAC 2007: 509-514 - [c22]Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou:
An efficient SAT-based path delay fault ATPG with an unified sensitization model. ITC 2007: 1-7 - [c21]Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang:
A prototype of a wireless-based test system. SoCC 2007: 225-228 - [c20]Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou:
Handling Pattern-Dependent Delay Faults in Diagnosis. VTS 2007: 151-157 - 2006
- [c19]Ying-Yen Chen, Jing-Jia Liou:
Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. DFT 2006: 428-438 - [c18]Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou:
Exploring linear structures of critical path delay faults to reduce test efforts. ICCAD 2006: 100-106 - 2005
- [c17]Ying-Yen Chen, Min-Pin Kuo, Jing-Jia Liou:
Diagnosis framework for locating failed segments of path delay faults. ITC 2005: 8 - [c16]Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu:
A BIST Scheme for FPGA Interconnect Delay Faults. VTS 2005: 201-206 - 2004
- [j3]Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng:
Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1550-1565 (2004) - [c15]Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT 2004: 478-486 - 2003
- [j2]Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting (Tim) Cheng:
Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3038-3048 (2003) - [j1]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 756-769 (2003) - [c14]Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng:
Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC 2003: 751-756 - [c13]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak:
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673 - [c12]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE 2003: 10328-10335 - [c11]Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang:
On Structural vs. Functional Testing for Delay Faults. ISQED 2003: 438-441 - [c10]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou:
Diagnosis of Delay Defects Using Statistical Timing Models. VTS 2003: 339-344 - 2002
- [c9]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 - [c8]Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng:
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC 2002: 566-569 - [c7]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng:
On theoretical and practical considerations of path selection for delay fault testing. ICCAD 2002: 94-100 - [c6]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 - 2001
- [c5]Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC 2001: 661-666 - [c4]Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng:
Delay testing considering crosstalk-induced effects. ITC 2001: 558-567 - 2000
- [c3]Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu:
Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC 2000: 587-592 - [c2]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD 2000: 493-496 - [c1]Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee:
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. VTS 2000: 97-104
Coauthor Index
aka: Kwang-Ting (Tim) Cheng
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