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2010 – 2019
- 2016
[j10]Sangmin Kim, Seungwhun Paik, Seokhyeong Kang, Youngsoo Shin:
Wakeup scheduling and its buffered tree synthesis for power gating circuits. Integr. 53: 157-170 (2016)- 2014
- [j9]Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik:
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 146-159 (2014) - 2012
- [j8]Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin:
Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1019-1030 (2012) - [j7]Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin:
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 593-604 (2012) - 2011
- [j6]Youngsoo Shin, Seungwhun Paik:
Pulsed-Latch Circuits: A New Dimension in ASIC Design. IEEE Des. Test Comput. 28(6): 50-57 (2011) - [j5]Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin:
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20(8): 1547-1569 (2011) - [j4]Seungwhun Paik, Seonggwan Lee, Youngsoo Shin:
Retiming Pulsed-Latch Circuits With Regulating Pulse Width. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1114-1127 (2011) - [c12]Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin:
Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC 2011: 190-195 - [c11]Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin:
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC 2011: 376-381 - [c10]Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin:
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. ICCAD 2011: 640-646 - 2010
- [j3]Hyein Lee, Seungwhun Paik, Youngsoo Shin:
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 355-366 (2010) - [j2]Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin:
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 657-670 (2010) - [c9]Jun Seomun, Seungwhun Paik, Youngsoo Shin:
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ASP-DAC 2010: 581-586 - [c8]Seungwhun Paik, Lee-eun Yu, Youngsoo Shin:
Statistical time borrowing for pulsed-latch circuit designs. ASP-DAC 2010: 675-680 - [c7]Seungwhun Paik, Sangmin Kim, Youngsoo Shin:
Wakeup synthesis and its buffered tree construction for power gating circuit designs. ISLPED 2010: 413-418
2000 – 2009
- 2009
- [j1]Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim:
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 327-339 (2009) - [c6]Insup Shin, Seungwhun Paik, Youngsoo Shin:
Register allocation for high-level synthesis using dual supply voltages. DAC 2009: 937-942 - [c5]Seungwhun Paik, Insup Shin, Youngsoo Shin:
HLS-l: High-level synthesis of high performance latch-based circuits. DATE 2009: 1112-1117 - [c4]Seonggwan Lee, Seungwhun Paik, Youngsoo Shin:
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. ICCAD 2009: 375-380 - 2008
- [c3]Jinseob Jeong, Seungwhun Paik, Youngsoo Shin:
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. ASP-DAC 2008: 629-634 - [c2]Seungwhun Paik, Youngsoo Shin:
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. DAC 2008: 600-605 - [c1]Hyein Lee, Seungwhun Paik, Youngsoo Shin:
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ICCAD 2008: 224-229
Coauthor Index
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