default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDTaewhan Kim
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Taewhan Kim 0001
![[0000-0002-6114-3772]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-6114-3772")
— Seoul National University, Department of Electrical and Computer Engineering, Seoul, Korea (and 2 more) - Taewhan Kim 0002 — Yonsei University, Seoul, Korea
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[c43]Soeun Lee, Si-Woo Kim, Taewhan Kim, Dong-Jin Kim:
IFCap: Image-like Retrieval and Frequency-based Entity Filtering for Zero-shot Captioning. EMNLP 2024: 20715-20727- [i1]Kaichen Zhou, Yang Cao, Taewhan Kim, Hao Zhao, Hao Dong, Kai Ming Ting, Ye Zhu:
RAD: A Dataset and Benchmark for Real-Life Anomaly Detection with Robotic Observations. CoRR abs/2410.00713 (2024) - 2022
- [j28]Jongsung Kang, Taewhan Kim:
Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks. J. Comput. Sci. Eng. 16(2): 79-87 (2022) - [c42]Jaehoon Ahn, Taewhan Kim:
Neural Network Model for Detour Net Prediction. SLIP 2022: 6:1-6:5 - 2021
- [j27]Changho Han, Taewhan Kim:
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits. Integr. 78: 1-10 (2021) - 2020
- [j26]Taewhan Kim, Kangsoo Jung, Seog Park:
Sparsity Reduction Technique Using Grouping Method for Matrix Factorization in Differentially Private Recommendation Systems. IEICE Trans. Inf. Syst. 103-D(7): 1683-1692 (2020) - [j25]Jongsung Kang, Taewhan Kim:
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks. Integr. 71: 76-85 (2020) - [c41]Byungmin Ahn, Taewhan Kim:
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks. DATE 2020: 73-78
2010 – 2019
- 2019
- [c40]Gyoung-Hwan Hyun, Taewhan Kim:
Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. ICCAD 2019: 1-6 - [c39]Gyoung-Hwan Hyun, Taewhan Kim:
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits. ICCAD 2019: 1-6 - 2018
- [j24]Youngchan Kim, Taewhan Kim:
Synthesis and exploration of clock spines. IET Comput. Digit. Tech. 12(5): 241-248 (2018) - [c38]Juyeon Kim, Taewhan Kim:
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network. ISQED 2018: 31-36 - [c37]Joohan Kim, Taewhan Kim:
Clock buffer and flip-flop co-optimization for reducing peak current noise. ISQED 2018: 94-99 - [c36]Byungmin Ahn, Taewhan Kim:
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks. SoCC 2018: 221-226 - 2017
- [j23]Joohan Kim, Taewhan Kim:
Boundary optimization of buffered clock trees for low power. Integr. 56: 86-95 (2017) - [j22]Hyoungseok Moon, Taewhan Kim:
Loosely coupled multi-bit flip-flop allocation for power reduction. Integr. 58: 125-133 (2017) - [c35]Youngchan Kim, Taewhan Kim:
Algorithm for synthesis and exploration of clock spines. ASP-DAC 2017: 263-268 - [c34]Dongyoun Yi, Taewhan Kim:
Switch cell optimization of power-gated modern system-on-chips. ICCAD 2017: 555-560 - 2016
- [j21]Hyoungjun Jeon, Taewhan Kim:
Grey-level context-driven histogram equalisation. IET Image Process. 10(5): 349-358 (2016) - [c33]Hyoungseok Moon, Taewhan Kim:
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. ASP-DAC 2016: 268-273 - 2015
- [j20]Lu Cai, Taewhan Kim:
Context-driven hybrid image inpainting. IET Image Process. 9(10): 866-873 (2015) - [c32]Juyeon Kim, Taewhan Kim:
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. ASP-DAC 2015: 466-471 - 2014
- [j19]Byunghyun Lee, Taewhan Kim:
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs. Integr. 47(2): 184-194 (2014) - [j18]Sangdo Park, Taewhan Kim:
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis. Integr. 47(4): 476-486 (2014) - [c31]Myung Woo Lee, Taewhan Kim:
Fast algorithm of low power image reformation for OLED display. ICDIP 2014: 91591H - [c30]Hyungjung Seo, Taewhan Kim:
Post-silicon tunable clock buffer allocation based on fast chip yield computation. ISQED 2014: 490-495 - [c29]Sangdo Park, Taewhan Kim:
Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs. MWSCAS 2014: 511-514 - 2013
- [j17]Jongyoon Jung, Taewhan Kim:
Statistical Viability Analysis for Detecting False Paths Under Delay Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 111-123 (2013) - [c28]Byunghyun Lee, Taewhan Kim:
High-level TSV resource sharing and optimization for TSV based 3D IC designs. SoCC 2013: 153-158 - 2012
- [j16]Hyungjung Seo, Jaewon Seo, Taewhan Kim:
Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling. Comput. J. 55(11): 1367-1382 (2012) - [j15]Jongyoon Jung, Taewhan Kim:
Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1684-1697 (2012) - [c27]Kiyoung Kim, Taewhan Kim:
Algorithm for synthesizing design context-aware fast carry-skip adders. ASP-DAC 2012: 795-800 - [c26]Sangdo Park, Taewhan Kim:
Die matching algorithm for enhancing parametric yield of 3D ICs. ISOCC 2012: 143-146 - 2011
- [j14]Jongyoon Jung, Taewhan Kim:
Scheduling and Resource Binding Algorithm Considering Timing Variation. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 205-216 (2011) - [j13]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 494-498 (2011) - [c25]Kyoung-Hwan Lim, Taewhan Kim:
An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ASP-DAC 2011: 503-508 - [c24]Yongho Lee, Taewhan Kim:
A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. ASP-DAC 2011: 603-608 - [c23]Joohan Kim, Taewhan Kim:
A fine-grained timing driven synthesis of arithmetic circuits. ISOCC 2011: 80-83 - [c22]Sangdo Park, Taewhan Kim:
An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead. ISOCC 2011: 381-384 - 2010
- [j12]HaNeul Chon, Taewhan Kim:
Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC. Comput. J. 53(7): 883-894 (2010) - [j11]Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin:
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 657-670 (2010) - [c21]Yongho Lee, Taewhan Kim:
Technique for controlling power-mode transition noise in distributed sleep transistor network. ASP-DAC 2010: 131-136 - [c20]Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim:
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. ICCAD 2010: 361-364 - [c19]Minseok Kang, Taewhan Kim:
Clock buffer polarity assignment considering the effect of delay variations. ISQED 2010: 69-74
2000 – 2009
- 2009
- [j10]Benjamin Carrión Schäfer, Taewhan Kim:
Autonomous temperature control technique in VLSI circuits through logic replication. IET Comput. Digit. Tech. 3(1): 62-71 (2009) - [j9]Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim:
Interconnect and communication synthesis for distributed register-file microarchitecture. IET Comput. Digit. Tech. 3(2): 162-174 (2009) - [c18]HaNeul Chon, Taewhan Kim:
Timing variation-aware task scheduling and binding for MPSoC. ASP-DAC 2009: 137-142 - [c17]Jongyoon Jung, Taewhan Kim:
Timing variation-aware high-level synthesis considering accurate yield computation. ICCD 2009: 207-212 - 2008
- [j8]Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi:
Introduction to embedded systems week 2006 special issue. ACM Trans. Embed. Comput. Syst. 7(2): 8:1-8:3 (2008) - [j7]Benjamin Carrión Schäfer, Taewhan Kim:
Hotspots Elimination and Temperature Flattening in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1475-1487 (2008) - [c16]Jongyoon Jung, Taewhan Kim:
Timing variation-aware high level synthesis: Current results and research challenges. APCCAS 2008: 1004-1007 - [c15]Byunghyun Lee, Taewhan Kim:
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. ASP-DAC 2008: 703-707 - [c14]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. ICCAD 2008: 169-172 - [c13]Yesin Ryu, Taewhan Kim:
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. ICCAD 2008: 416-419 - [c12]Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin:
Power-gating-aware high-level synthesis. ISLPED 2008: 39-44 - 2007
- [j6]Yongseok Choi, Naehyuck Chang, Taewhan Kim:
DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1367-1381 (2007) - [c11]Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim:
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. DAC 2007: 765-770 - [c10]Jongyoon Jung, Taewhan Kim:
Timing variation-aware high-level synthesis. ICCAD 2007: 424-428 - [c9]Zhenmin Li, Taewhan Kim:
Address Code Optimization Exploiting Code Scheduling in DSP Applications. ISCAS 2007: 1573-1576 - [c8]Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim:
Temperature-Aware Compilation for VLIWProcessors. RTCSA 2007: 426-431 - [e2]Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro:
Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007 [contents] - 2006
- [j5]Jaewon Seo, Taewhan Kim, Joonwon Lee:
Optimal intratask dynamic voltage-scaling technique and its practical extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 47-57 (2006) - [j4]Jong-U. Shin, Taewhan Kim:
Technique for Transition Energy-Aware Dynamic Voltage Assignment. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 956-960 (2006) - [e1]Seongsoo Hong, Wayne H. Wolf, Krisztián Flautner, Taewhan Kim:
Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006. ACM 2006, ISBN 1-59593-543-6 [contents] - 2005
- [j3]Woo-Cheol Kwon, Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors. ACM Trans. Embed. Comput. Syst. 4(1): 211-230 (2005) - [c7]Yongseok Choi, Naehyuck Chang, Taewhan Kim:
DC-DC converter-aware power management for battery-operated embedded systems. DAC 2005: 895-900 - [c6]Jaewon Seo, Taewhan Kim, Nikil D. Dutt:
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD 2005: 450-455 - 2003
- [j2]Sungpack Hong, Taewhan Kim:
Bus Optimization for Low Power in High-Level Synthesis. J. Circuits Syst. Comput. 12(1): 1-18 (2003) - [j1]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 928-938 (2003) - [c5]Woo-Cheol Kwon, Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors. DAC 2003: 125-130 - 2002
- [c4]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC 2002: 608-611 - [c3]Jaewon Seo, Taewhan Kim:
Memory exploration utilizing scheduling effects in high-level synthesis. ISCAS (4) 2002: 73-76 - 2000
- [c2]Gernot Koch, Taewhan Kim, Reiner Genevriere:
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. ICCAD 2000: 33-38 - [c1]Sungpack Hong, Taewhan Kim:
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. ICCAD 2000: 312-317
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-18 19:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
