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ORCIDM. Ray Mercer
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- affiliation: Texas A&M University, College Station, Texas, USA
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Journal Articles
- 2001
[j12]Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
:
Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Des. Test Comput. 18(1): 31-41 (2001)- 1996
- [j11]Chanhee Oh, M. Ray Mercer:
Efficient logic-level timing analysis using constraint-guided critical path search. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 346-355 (1996) - 1994
- [j10]Mark A. Heap, M. Ray Mercer:
Least Upper Bounds an OBDD Sizes. IEEE Trans. Computers 43(6): 764-767 (1994) - 1992
- [j9]Eun Sei Park, M. Ray Mercer, Thomas W. Williams:
The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41(6): 688-698 (1992) - [j8]Rohit Kapur, M. Ray Mercer:
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41(12): 1580-1588 (1992) - [j7]Eun Sei Park, M. Ray Mercer:
An efficient delay test generation system for combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 926-938 (1992) - 1991
- [j6]M. Ray Mercer:
Testing and Design Verification of Electronic Components. Computer 24(9): 107-108 (1991) - [j5]Don E. Ross, Kenneth M. Butler, M. Ray Mercer:
Exact ordered binary decision diagram size when representing classes of symmetric functions. J. Electron. Test. 2(3): 243-259 (1991) - 1990
- [j4]M. Ray Mercer:
Guest Editorial: ITC 20th Anniversary. IEEE Des. Test Comput. 7(2): 2-3 (1990) - 1989
- [j3]Eun Sei Park, M. Ray Mercer, Thomas W. Williams:
A statistical model for delay-fault testing. IEEE Des. Test 6(1): 45-55 (1989) - 1988
- [j2]Tom E. Kirkland, M. Ray Mercer:
Algorithms for automatic test pattern generation. IEEE Des. Test 5(3): 43-55 (1988) - 1986
- [j1]Ki Soo Hwang, M. Ray Mercer:
Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 564-572 (1986)
Conference and Workshop Papers
- 2005
- [c60]Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer:
An optimal test pattern selection method to improve the defect coverage. ITC 2005: 9 - 2004
- [c59]Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer:
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. DATE 2004: 1066-1071 - [c58]Jennifer Dworak, James Wingfield, M. Ray Mercer:
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. DFT 2004: 460-468 - [c57]Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer:
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. VTS 2004: 9-15 - 2003
- [c56]Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer:
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. Asian Test Symposium 2003: 354-359 - [c55]James Wingfield, Jennifer Dworak, M. Ray Mercer:
Function-Based Dynamic Compaction and its Impact on Test Set Sizes. DFT 2003: 167-174 - [c54]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050 - 2002
- [c53]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 - [c52]Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer:
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. DATE 2002: 94-99 - [c51]Rohit Kapur, Thomas W. Williams, M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121 - [c50]Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT 2002: 177-185 - [c49]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 - 2000
- [c48]Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151- - [c47]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC 2000: 930-939 - 1999
- [c46]Ronald W. Mehler, M. Ray Mercer:
Multi-Level Logic Minimization through Fault Dictionary Analysis. ICCD 1999: 315-318 - [c45]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer:
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC 1999: 1031-1037 - [c44]Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer:
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS 1999: 268-274 - 1996
- [c43]Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC 1996: 578-583 - [c42]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
A Better ATPG Algorithm and Its Design Principles. ICCD 1996: 248-253 - [c41]Jaehong Park, M. Ray Mercer:
Using Functional Information and Strategy Switching in Sequential ATPG. ICCD 1996: 254-260 - [c40]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
Using Target Faults To Detect Non-Tartget Defects. ITC 1996: 629-638 - [c39]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 - 1995
- [c38]Jaehong Park, Chanhee Oh, M. Ray Mercer:
Improved sequential ATPG using functional observation information and new justification methods. ED&TC 1995: 262-266 - [c37]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
Enhanced testing performance via unbiased test sets. ED&TC 1995: 294-302 - [c36]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
On Efficiently and Reliably Achieving Low Defective Part Levels. ITC 1995: 616-625 - [c35]Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%. VTS 1995: 74-83 - 1994
- [c34]Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337 - [c33]Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams:
Limitations in predicting defect level based on stuck-at fault coverage. VTS 1994: 186-191 - 1993
- [c32]Jaehong Park, M. Ray Mercer:
An Efficient Symbolic Design Verification System. ICCD 1993: 294-298 - [c31]Eun Sei Park, M. Ray Mercer:
Switch-Level ATPG Using Constraint-Guided Line Justification. ITC 1993: 616-625 - [c30]Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer:
Combinational circuit ATPG using binary decision diagrams. VTS 1993: 251-258 - 1992
- [c29]M. Ray Mercer, Rohit Kapur, Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC 1992: 624-627 - [c28]Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage:
ETA: electrical-level timing analysis. ICCAD 1992: 258-262 - [c27]Mark A. Heap, William A. Rogers, M. Ray Mercer:
A Synthesis Algorithm for Two-Level XOR Based Circuits. ICCD 1992: 459-463 - [c26]Rohit Kapur, Jaehong Park, M. Ray Mercer:
All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC 1992: 762-769 - [c25]Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross:
The roles of controllability and observability in design for test. VTS 1992: 211-216 - 1991
- [c24]Thomas W. Williams, Bill Underwood, M. Ray Mercer:
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC 1991: 87-92 - [c23]Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer:
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC 1991: 417-420 - [c22]Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer:
Fast functional evaluation of candidate OBDD variable orderings. EURO-DAC 1991: 4-10 - [c21]Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs. ITC 1991: 897-905 - 1990
- [c20]Eun Sei Park, M. Ray Mercer:
An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC 1990: 522-528 - [c19]Kenneth M. Butler, M. Ray Mercer:
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. DAC 1990: 673-678 - 1989
- [c18]C. Thomas Glover, M. Ray Mercer:
A Deterministic Approach to Adjacency Testing for Delay Faults. DAC 1989: 351-356 - 1988
- [c17]C. Thomas Glover, M. Ray Mercer:
A Method of Delay Fault Test Generation. DAC 1988: 90-95 - [c16]Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler:
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. DAC 1988: 597-600 - [c15]Eun Sei Park, Thomas W. Williams, M. Ray Mercer:
Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC 1988: 492-499 - [c14]Steven P. Smith, Bill Underwood, M. Ray Mercer:
D^3FS: A Demand Driven Deductive Fault Simulator. ITC 1988: 582-592 - 1987
- [c13]Steven P. Smith, M. Ray Mercer, B. Brodk:
Demand Driven Simulation: BACKSIM. DAC 1987: 181-187 - [c12]Tom E. Kirkland, M. Ray Mercer:
A Topological Search Algorithm for ATPG. DAC 1987: 502-508 - 1986
- [c11]Tom E. Kirkland, M. Ray Mercer:
A Two-Level Guidance Heuristic for ATPG. FJCC 1986: 841-846 - [c10]Ki Soo Hwang, M. Ray Mercer:
Informed Test Generation Guidance Using Partially Specified Fanout Constraints. ITC 1986: 113-120 - [c9]M. Ray Mercer:
Logic Elements for Universally Testable Circuits. ITC 1986: 493-497 - [c8]Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood:
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. ITC 1986: 498-505 - [c7]Vishwani D. Agrawal, M. Ray Mercer:
Deterministic Versus Random Testing. ITC 1986: 718 - 1985
- [c6]Eric Schell, M. Ray Mercer:
CADTOOLS: a CAD algorithm development system. DAC 1985: 658-666 - [c5]John Salick, Bill Underwood, M. Ray Mercer:
Built-In Self Test Input Generator for Programmable Logic Arrays. ITC 1985: 115-125 - 1984
- [c4]Bill Underwood, M. Ray Mercer:
Correlating Testability with Fault Detection. ITC 1984: 697-704 - 1983
- [c3]M. Ray Mercer:
Testing Issues at the University of Texas. ITC 1983: 158-159 - 1982
- [c2]Vishwani D. Agrawal, M. Ray Mercer:
Testability Measures : What Do They Tell Us ? ITC 1982: 391-399 - 1981
- [c1]M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman:
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC 1981: 561-565
Coauthor Index
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